lincan/src/i82527.c

   1 /* i82527.c
   2  * Linux CAN-bus device driver.
   3  * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
   4  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
   5  * email:pisa@cmp.felk.cvut.cz
   6  * This software is released under the GPL-License.
   7  * Version lincan-0.2  9 Jul 2003
   8  */
   9
  10 #include "../include/can.h"
  11 #include "../include/can_sysdep.h"
  12 #include "../include/main.h"
  13 #include "../include/i82527.h"
  14
  15 void i82527_irq_rtr_handler(struct chip_t *chip, struct msgobj_t *obj,
  16                             struct rtr_id *rtr_search, unsigned long message_id);
  17
  18
  19 extern int stdmask;
  20 extern int extmask;
  21 extern int mo15mask;
  22
  23 /* helper functions for segmented cards read and write configuration and status registers
  24    above 0xf offset */
  25
  26 void i82527_seg_write_reg(const struct chip_t *chip, unsigned char data, unsigned address)
  27 {
  28         if((address > 0xf) && (chip->flags & CHIP_SEGMENTED))
  29                 canobj_write_reg(chip, chip->msgobj[(address>>4)-1],data, address & 0xf);
  30         else
  31                 can_write_reg(chip, data, address);
  32 }
  33
  34 unsigned i82527_seg_read_reg(const struct chip_t *chip, unsigned address)
  35 {
  36         if((address > 0xf) && (chip->flags & CHIP_SEGMENTED))
  37                 return canobj_read_reg(chip, chip->msgobj[(address>>4)-1], address & 0xf);
  38         else
  39                 return can_read_reg(chip, address);
  40 }
  41
  42 int i82527_enable_configuration(struct chip_t *chip)
  43 {
  44         unsigned short flags=0;
  45
  46         flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
  47         can_write_reg(chip, flags|iCTL_CCE, iCTL);
  48
  49         return 0;
  50 }
  51
  52 int i82527_disable_configuration(struct chip_t *chip)
  53 {
  54         unsigned short flags=0;
  55
  56         flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
  57         can_write_reg(chip, flags, iCTL);
  58
  59         return 0;
  60 }
  61
  62 int i82527_chip_config(struct chip_t *chip)
  63 {
  64         can_write_reg(chip,chip->int_cpu_reg,iCPU); // Configure cpu interface
  65         can_write_reg(chip,(iCTL_CCE|iCTL_INI),iCTL); // Enable configuration
  66         i82527_seg_write_reg(chip,chip->int_clk_reg,iCLK); // Set clock out slew rates
  67         i82527_seg_write_reg(chip,chip->int_bus_reg,iBUS); /* Bus configuration */
  68         can_write_reg(chip,0x00,iSTAT); /* Clear error status register */
  69
  70         /* Check if we can at least read back some arbitrary data from the
  71          * card. If we can not, the card is not properly configured!
  72          */
  73         canobj_write_reg(chip,chip->msgobj[1],0x25,iMSGDAT1);
  74         canobj_write_reg(chip,chip->msgobj[2],0x52,iMSGDAT3);
  75         canobj_write_reg(chip,chip->msgobj[10],0xc3,iMSGDAT6);
  76         if ( (canobj_read_reg(chip,chip->msgobj[1],iMSGDAT1) != 0x25) ||
  77               (canobj_read_reg(chip,chip->msgobj[2],iMSGDAT3) != 0x52) ||
  78               (canobj_read_reg(chip,chip->msgobj[10],iMSGDAT6) != 0xc3) ) {
  79                 CANMSG("Could not read back from the hardware.\n");
  80                 CANMSG("This probably means that your hardware is not correctly configured!\n");
  81                 return -1;
  82         }
  83         else
  84                 DEBUGMSG("Could read back, hardware is probably configured correctly\n");
  85
  86         if (chip->baudrate == 0)
  87                 chip->baudrate=1000000;
  88
  89         if (i82527_baud_rate(chip,chip->baudrate,chip->clock,0,75,0)) {
  90                 CANMSG("Error configuring baud rate\n");
  91                 return -ENODEV;
  92         }
  93         if (i82527_standard_mask(chip,0x0000,stdmask)) {
  94                 CANMSG("Error configuring standard mask\n");
  95                 return -ENODEV;
  96         }
  97         if (i82527_extended_mask(chip,0x00000000,extmask)) {
  98                 CANMSG("Error configuring extended mask\n");
  99                 return -ENODEV;
 100         }
 101         if (i82527_message15_mask(chip,0x00000000,mo15mask)) {
 102                 CANMSG("Error configuring message 15 mask\n");
 103                 return -ENODEV;
 104         }
 105         if (i82527_clear_objects(chip)) {
 106                 CANMSG("Error clearing message objects\n");
 107                 return -ENODEV;
 108         }
 109         if (i82527_config_irqs(chip,iCTL_IE|iCTL_EIE)) { /* has been 0x0a */
 110                 CANMSG("Error configuring interrupts\n");
 111                 return -ENODEV;
 112         }
 113
 114         return 0;
 115 }
 116
 117 /* Set communication parameters.
 118  * param rate baud rate in Hz
 119  * param clock frequency of i82527 clock in Hz (ISA osc is 14318000)
 120  * param sjw synchronization jump width (0-3) prescaled clock cycles
 121  * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
 122  * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
 123  */
 124 int i82527_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
 125                                                         int sampl_pt, int flags)
 126 {
 127         int best_error = 1000000000, error;
 128         int best_tseg=0, best_brp=0, best_rate=0, brp=0;
 129         int tseg=0, tseg1=0, tseg2=0;
 130
 131         if (i82527_enable_configuration(chip))
 132                 return -ENODEV;
 133
 134         clock /=2;
 135
 136         /* tseg even = round down, odd = round up */
 137         for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
 138                 brp = clock/((1+tseg/2)*rate)+tseg%2;
 139                 if (brp == 0 || brp > 64)
 140                         continue;
 141                 error = rate - clock/(brp*(1+tseg/2));
 142                 if (error < 0)
 143                         error = -error;
 144                 if (error <= best_error) {
 145                         best_error = error;
 146                         best_tseg = tseg/2;
 147                         best_brp = brp-1;
 148                         best_rate = clock/(brp*(1+tseg/2));
 149                 }
 150         }
 151         if (best_error && (rate/best_error < 10)) {
 152                 CANMSG("baud rate %d is not possible with %d Hz clock\n",
 153                                                                 rate, 2*clock);
 154                 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
 155                                 best_rate, best_brp, best_tseg, tseg1, tseg2);
 156                 return -EINVAL;
 157         }
 158         tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
 159         if (tseg2 < 0)
 160                 tseg2 = 0;
 161         if (tseg2 > MAX_TSEG2)
 162                 tseg2 = MAX_TSEG2;
 163
 164         tseg1 = best_tseg-tseg2-2;
 165         if (tseg1>MAX_TSEG1) {
 166                 tseg1 = MAX_TSEG1;
 167                 tseg2 = best_tseg-tseg1-2;
 168         }
 169
 170         DEBUGMSG("Setting %d bps.\n", best_rate);
 171         DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
 172                                         best_brp, best_tseg, tseg1, tseg2,
 173                                         (100*(best_tseg-tseg2)/(best_tseg+1)));
 174
 175
 176         i82527_seg_write_reg(chip, sjw<<6 | best_brp, iBT0);
 177         can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | tseg2<<4 | tseg1,
 178                                                                 iBT1);
 179         DEBUGMSG("Writing 0x%x to iBT0\n",(sjw<<6 | best_brp));
 180         DEBUGMSG("Writing 0x%x to iBT1\n",((flags & BTR1_SAM) != 0)<<7 |
 181                                                         tseg2<<4 | tseg1);
 182
 183         i82527_disable_configuration(chip);
 184
 185         return 0;
 186 }
 187
 188 int i82527_standard_mask(struct chip_t *chip, unsigned short code, unsigned short mask)
 189 {
 190         unsigned char mask0, mask1;
 191
 192         mask0 = (unsigned char) (mask >> 3);
 193         mask1 = (unsigned char) (mask << 5);
 194
 195         can_write_reg(chip,mask0,iSGM0);
 196         can_write_reg(chip,mask1,iSGM1);
 197
 198         DEBUGMSG("Setting standard mask to 0x%lx\n",(unsigned long)mask);
 199
 200         return 0;
 201 }
 202
 203 int i82527_extended_mask(struct chip_t *chip, unsigned long code, unsigned long mask)
 204 {
 205         unsigned char mask0, mask1, mask2, mask3;
 206
 207         mask0 = (unsigned char) (mask >> 21);
 208         mask1 = (unsigned char) (mask >> 13);
 209         mask2 = (unsigned char) (mask >> 5);
 210         mask3 = (unsigned char) (mask << 3);
 211
 212         can_write_reg(chip,mask0,iEGM0);
 213         can_write_reg(chip,mask1,iEGM1);
 214         can_write_reg(chip,mask2,iEGM2);
 215         can_write_reg(chip,mask3,iEGM3);
 216
 217         DEBUGMSG("Setting extended mask to 0x%lx\n",(unsigned long)mask);
 218
 219         return 0;
 220 }
 221
 222 int i82527_message15_mask(struct chip_t *chip, unsigned long code, unsigned long mask)
 223 {
 224         unsigned char mask0, mask1, mask2, mask3;
 225
 226         mask0 = (unsigned char) (mask >> 21);
 227         mask1 = (unsigned char) (mask >> 13);
 228         mask2 = (unsigned char) (mask >> 5);
 229         mask3 = (unsigned char) (mask << 3);
 230
 231         can_write_reg(chip,mask0,i15M0);
 232         can_write_reg(chip,mask1,i15M1);
 233         can_write_reg(chip,mask2,i15M2);
 234         can_write_reg(chip,mask3,i15M3);
 235
 236         DEBUGMSG("Setting message 15 mask to 0x%lx\n",mask);
 237
 238         return 0;
 239
 240
 241 }
 242
 243 int i82527_clear_objects(struct chip_t *chip)
 244 {
 245         int i=0,id=0,data=0;
 246         struct msgobj_t *obj;
 247
 248         DEBUGMSG("Cleared all message objects on chip\n");
 249
 250         for (i=1; i<=15; i++) {
 251                 obj=chip->msgobj[i];
 252                 canobj_write_reg(chip,obj,(INTPD_RES|RXIE_RES|TXIE_RES|MVAL_RES),iMSGCTL0);
 253                 canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
 254                 for (data=0x07; data<0x0f; data++)
 255                         canobj_write_reg(chip,obj,0x00,data);
 256                 for (id=2; id<6; id++) {
 257                         canobj_write_reg(chip,obj,0x00,id);
 258                 }
 259                 if (extended==0) {
 260                         canobj_write_reg(chip,obj,0x00,iMSGCFG);
 261                 }
 262                 else {
 263                         canobj_write_reg(chip,obj,MCFG_XTD,iMSGCFG);
 264                 }
 265         }
 266         if (extended==0)
 267                 DEBUGMSG("All message ID's set to standard\n");
 268         else
 269                 DEBUGMSG("All message ID's set to extended\n");
 270
 271         return 0;
 272 }
 273
 274 int i82527_config_irqs(struct chip_t *chip, short irqs)
 275 {
 276         can_write_reg(chip,irqs,iCTL);
 277         DEBUGMSG("Configured hardware interrupt delivery\n");
 278         return 0;
 279 }
 280
 281 int i82527_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
 282 {
 283         if (extended) {
 284                 canobj_write_reg(chip,obj,MCFG_XTD,iMSGCFG);
 285         }
 286         else {
 287                 canobj_write_reg(chip,obj,0x00,iMSGCFG);
 288         }
 289         canobj_write_reg(chip,obj,(NEWD_RES|MLST_RES|TXRQ_RES|RMPD_RES), iMSGCTL1);
 290         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
 291
 292         DEBUGMSG("i82527_pre_read_config: configured obj at 0x%08lx\n",obj->obj_base_addr);
 293
 294
 295         return 0;
 296 }
 297
 298 int i82527_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
 299                                                         struct canmsg_t *msg)
 300 {
 301         int i=0,id0=0,id1=0,id2=0,id3=0;
 302         int len;
 303
 304         len = msg->length;
 305         if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
 306
 307         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
 308         canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_SET|NEWD_RES),iMSGCTL1);
 309
 310         if (extended || (msg->flags&MSG_EXT)) {
 311                 canobj_write_reg(chip,obj,(len<<4)|(MCFG_DIR|MCFG_XTD),iMSGCFG);
 312                 id0 = (unsigned char) (msg->id<<3);
 313                 id1 = (unsigned char) (msg->id>>5);
 314                 id2 = (unsigned char) (msg->id>>13);
 315                 id3 = (unsigned char) (msg->id>>21);
 316                 canobj_write_reg(chip,obj,id0,iMSGID3);
 317                 canobj_write_reg(chip,obj,id1,iMSGID2);
 318                 canobj_write_reg(chip,obj,id2,iMSGID1);
 319                 canobj_write_reg(chip,obj,id3,iMSGID0);
 320         }
 321         else {
 322                 canobj_write_reg(chip,obj,(len<<4)|MCFG_DIR,iMSGCFG);
 323                 id1 = (unsigned char) (msg->id<<5);
 324                 id0 = (unsigned char) (msg->id>>3);
 325                 canobj_write_reg(chip,obj,id1,iMSGID1);
 326                 canobj_write_reg(chip,obj,id0,iMSGID0);
 327         }
 328         canobj_write_reg(chip,obj,RMPD_UNC|TXRQ_UNC|CPUU_SET|NEWD_SET,iMSGCTL1);
 329         for (i=0; i<len; i++) {
 330                 canobj_write_reg(chip,obj,msg->data[i],iMSGDAT0+i);
 331         }
 332
 333         return 0;
 334 }
 335
 336 int i82527_send_msg(struct chip_t *chip, struct msgobj_t *obj,
 337                                                         struct canmsg_t *msg)
 338 {
 339         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_SET|RXIE_RES|INTPD_RES),iMSGCTL0);
 340
 341         if (msg->flags & MSG_RTR) {
 342                 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|CPUU_RES|NEWD_SET),iMSGCTL1);
 343         }
 344         else {
 345                 canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_SET|CPUU_RES|NEWD_SET),iMSGCTL1);
 346         }
 347
 348         return 0;
 349 }
 350
 351 int i82527_check_tx_stat(struct chip_t *chip)
 352 {
 353         if (can_read_reg(chip,iSTAT) & iSTAT_TXOK) {
 354                 can_write_reg(chip,0x0,iSTAT);
 355                 return 0;
 356         }
 357         else {
 358                 can_write_reg(chip,0x0,iSTAT);
 359                 return 1;
 360         }
 361 }
 362
 363 int i82527_remote_request(struct chip_t *chip, struct msgobj_t *obj)
 364 {
 365         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
 366         canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_SET|MLST_RES|NEWD_RES),iMSGCTL1);
 367
 368         return 0;
 369 }
 370
 371 int i82527_set_btregs(struct chip_t *chip, unsigned short btr0,
 372                                                         unsigned short btr1)
 373 {
 374         if (i82527_enable_configuration(chip))
 375                 return -ENODEV;
 376
 377         i82527_seg_write_reg(chip, btr0, iBT0);
 378         i82527_seg_write_reg(chip, btr1, iBT1);
 379
 380         i82527_disable_configuration(chip);
 381
 382         return 0;
 383 }
 384
 385 int i82527_start_chip(struct chip_t *chip)
 386 {
 387         unsigned short flags = 0;
 388
 389         flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
 390         can_write_reg(chip, flags, iCTL);
 391
 392         return 0;
 393 }
 394
 395 int i82527_stop_chip(struct chip_t *chip)
 396 {
 397         unsigned short flags = 0;
 398
 399         flags = can_read_reg(chip, iCTL) & (iCTL_IE|iCTL_SIE|iCTL_EIE);
 400         can_write_reg(chip, flags|(iCTL_CCE|iCTL_INI), iCTL);
 401
 402         return 0;
 403 }
 404
 405 inline void i82527_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
 406 {
 407         int cmd;
 408
 409         canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
 410
 411         if(obj->tx_slot){
 412                 /* Do local transmitted message distribution if enabled */
 413                 if (processlocal){
 414                         obj->tx_slot->msg.flags |= MSG_LOCAL;
 415                         canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
 416                 }
 417                 /* Free transmitted slot */
 418                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 419                 obj->tx_slot=NULL;
 420         }
 421
 422         cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
 423         if(cmd<0)
 424                 return;
 425
 426         if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
 427                 obj->ret = -1;
 428                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
 429                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 430                 obj->tx_slot=NULL;
 431                 return;
 432         }
 433         if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
 434                 obj->ret = -1;
 435                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
 436                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 437                 obj->tx_slot=NULL;
 438                 return;
 439         }
 440 }
 441
 442 inline void i82527_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj, int objnum)
 443 {
 444         int i;
 445         unsigned long message_id;
 446         int msgcfg, msgctl1;
 447
 448         msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
 449         if(msgctl1 & NEWD_RES)
 450                 return;
 451
 452         do {
 453                 if(objnum != 14) {
 454                         canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_UNC|NEWD_RES),iMSGCTL1);
 455                         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
 456                 }
 457
 458                 msgcfg = canobj_read_reg(chip,obj,iMSGCFG);
 459
 460                 if (msgcfg&MCFG_XTD) {
 461                         message_id =canobj_read_reg(chip,obj,iMSGID3);
 462                         message_id|=canobj_read_reg(chip,obj,iMSGID2)<<8;
 463                         message_id|=canobj_read_reg(chip,obj,iMSGID1)<<16;
 464                         message_id|=canobj_read_reg(chip,obj,iMSGID0)<<24;
 465                         message_id>>=3;
 466                         obj->rx_msg.flags = MSG_EXT;
 467
 468                 }
 469                 else {
 470                         message_id =canobj_read_reg(chip,obj,iMSGID1);
 471                         message_id|=canobj_read_reg(chip,obj,iMSGID0)<<8;
 472                         message_id>>=5;
 473                         obj->rx_msg.flags = 0;
 474                 }
 475
 476                 obj->rx_msg.length = (msgcfg >> 4) & 0xf;
 477                 if(obj->rx_msg.length > CAN_MSG_LENGTH) obj->rx_msg.length = CAN_MSG_LENGTH;
 478
 479                 obj->rx_msg.id = message_id;
 480
 481                 for (i=0; i < obj->rx_msg.length; i++)
 482                         obj->rx_msg.data[i] = canobj_read_reg(chip,obj,iMSGDAT0+i);
 483
 484
 485                 if(objnum != 14) {
 486                         /* if NEWD is set after data read, then read data are likely inconsistent */
 487                         msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
 488                         if(msgctl1 & NEWD_SET) {
 489                                 CANMSG("i82527_irq_read_handler: object %d data overwritten\n",objnum);
 490                                 continue;
 491                         }
 492                 }
 493                 else {
 494                         /* this object is special and data are queued in the shadow register */
 495                         canobj_write_reg(chip,obj,(MVAL_SET|TXIE_RES|RXIE_SET|INTPD_RES),iMSGCTL0);
 496                         canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_UNC|NEWD_RES),iMSGCTL1);
 497                         msgctl1=canobj_read_reg(chip,obj,iMSGCTL1);
 498                 }
 499
 500
 501                 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
 502
 503                 if (msgctl1 & NEWD_SET)
 504                         continue;
 505
 506                 if (msgctl1 & MLST_SET) {
 507                         canobj_write_reg(chip,obj,(RMPD_UNC|TXRQ_UNC|MLST_RES|NEWD_UNC),iMSGCTL1);
 508                         CANMSG("i82527_irq_read_handler: object %d message lost\n",objnum);
 509                 }
 510
 511                 return;
 512
 513         } while(1);
 514 }
 515
 516 /*
 517                         if (msgcfg&MCFG_XTD) {
 518                                 message_id =canobj_read_reg(chip,obj,iMSGID3);
 519                                 message_id|=canobj_read_reg(chip,obj,iMSGID2)<<8;
 520                                 message_id|=canobj_read_reg(chip,obj,iMSGID1)<<16;
 521                                 message_id|=canobj_read_reg(chip,obj,iMSGID0)<<24;
 522                                 message_id>>=3;
 523                         }
 524                         else {
 525                                 message_id =canobj_read_reg(chip,obj,iMSGID1);
 526                                 message_id|=canobj_read_reg(chip,obj,iMSGID0)<<8;
 527                                 message_id>>=5;
 528                         }
 529
 530                         can_spin_lock(&hardware_p->rtr_lock);
 531                         rtr_search=hardware_p->rtr_queue;
 532                         while (rtr_search != NULL) {
 533                                 if (rtr_search->id == message_id)
 534                                         break;
 535                                 rtr_search=rtr_search->next;
 536                         }
 537                         can_spin_unlock(&hardware_p->rtr_lock);
 538                         if ((rtr_search!=NULL) && (rtr_search->id==message_id))
 539                                 i82527_irq_rtr_handler(chip, obj, rtr_search, message_id);
 540                         else
 541                                 i82527_irq_read_handler(chip, obj, message_id);
 542 */
 543
 544 can_irqreturn_t i82527_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 545 {
 546         unsigned char msgcfg;
 547
 548         unsigned irq_register;
 549         unsigned object;
 550         struct chip_t *chip=(struct chip_t *)dev_id;
 551         struct msgobj_t *obj;
 552
 553         /*put_reg=device->hwspecops->write_register;*/
 554         /*get_reg=device->hwspecops->read_register;*/
 555
 556         irq_register = i82527_seg_read_reg(chip, iIRQ);
 557
 558         if(!irq_register) {
 559                 DEBUGMSG("i82527: spurious IRQ\n");
 560                 return CAN_IRQ_NONE;
 561         }
 562
 563
 564         do {
 565
 566                 DEBUGMSG("i82527: iIRQ 0x%02x\n",irq_register);
 567
 568                 if (irq_register == 0x01) {
 569                         DEBUGMSG("Status register: 0x%x\n",can_read_reg(chip, iSTAT));
 570                         continue;
 571                         /*return CAN_IRQ_NONE;*/
 572                 }
 573
 574                 if (irq_register == 0x02)
 575                         object = 14;
 576                 else if(irq_register < 14)
 577                         object = irq_register-3;
 578                 else
 579                         return CAN_IRQ_NONE;
 580
 581                 obj=chip->msgobj[object];
 582
 583                 msgcfg = canobj_read_reg(chip,obj,iMSGCFG);
 584                 if (msgcfg & MCFG_DIR) {
 585                         can_msgobj_set_fl(obj,TX_REQUEST);
 586                         while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
 587                                 can_msgobj_clear_fl(obj,TX_REQUEST);
 588
 589                                 if(canobj_read_reg(chip,obj,iMSGCTL1)&TXRQ_RES)
 590                                         i82527_irq_write_handler(chip, obj);
 591
 592                                 can_msgobj_clear_fl(obj,TX_LOCK);
 593                                 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
 594                         }
 595                 }
 596                 else {
 597
 598                         i82527_irq_read_handler(chip, obj, object);
 599                 }
 600
 601         } while((irq_register=i82527_seg_read_reg(chip, iIRQ)) != 0);
 602
 603         return CAN_IRQ_HANDLED;
 604 }
 605
 606 void i82527_irq_rtr_handler(struct chip_t *chip, struct msgobj_t *obj,
 607                             struct rtr_id *rtr_search, unsigned long message_id)
 608 {
 609         short int i=0;
 610
 611         canobj_write_reg(chip,obj,(MVAL_RES|TXIE_RES|RXIE_RES|INTPD_RES),iMSGCTL0);
 612         canobj_write_reg(chip,obj,(RMPD_RES|TXRQ_RES|MLST_RES|NEWD_RES),iMSGCTL1);
 613
 614         can_spin_lock(&hardware_p->rtr_lock);
 615
 616         rtr_search->rtr_message->id=message_id;
 617         rtr_search->rtr_message->length=(canobj_read_reg(chip,obj,iMSGCFG) & 0xf0)>>4;
 618         for (i=0; i<rtr_search->rtr_message->length; i++)
 619                 rtr_search->rtr_message->data[i]=canobj_read_reg(chip,obj,iMSGDAT0+i);
 620
 621         can_spin_unlock(&hardware_p->rtr_lock);
 622
 623         if (waitqueue_active(&rtr_search->rtr_wq))
 624                 wake_up(&rtr_search->rtr_wq);
 625 }
 626
 627 int i82527_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj)
 628 {
 629         can_preempt_disable();
 630
 631         can_msgobj_set_fl(obj,TX_REQUEST);
 632         while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
 633                 can_msgobj_clear_fl(obj,TX_REQUEST);
 634
 635                 if(canobj_read_reg(chip,obj,iMSGCTL1)&TXRQ_RES)
 636                         i82527_irq_write_handler(chip, obj);
 637
 638                 can_msgobj_clear_fl(obj,TX_LOCK);
 639                 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
 640         }
 641
 642         can_preempt_enable();
 643         return 0;
 644 }
 645
 646 int i82527_register(struct chipspecops_t *chipspecops)
 647 {
 648         chipspecops->chip_config = i82527_chip_config;
 649         chipspecops->baud_rate = i82527_baud_rate;
 650         chipspecops->standard_mask = i82527_standard_mask;
 651         chipspecops->extended_mask = i82527_extended_mask;
 652         chipspecops->message15_mask = i82527_message15_mask;
 653         chipspecops->clear_objects = i82527_clear_objects;
 654         chipspecops->config_irqs = i82527_config_irqs;
 655         chipspecops->pre_read_config = i82527_pre_read_config;
 656         chipspecops->pre_write_config = i82527_pre_write_config;
 657         chipspecops->send_msg = i82527_send_msg;
 658         chipspecops->check_tx_stat = i82527_check_tx_stat;
 659         chipspecops->wakeup_tx = i82527_wakeup_tx;
 660         chipspecops->remote_request = i82527_remote_request;
 661         chipspecops->enable_configuration = i82527_enable_configuration;
 662         chipspecops->disable_configuration = i82527_disable_configuration;
 663         chipspecops->set_btregs = i82527_set_btregs;
 664         chipspecops->start_chip = i82527_start_chip;
 665         chipspecops->stop_chip = i82527_stop_chip;
 666         chipspecops->irq_handler = i82527_irq_handler;
 667         return 0;
 668 }