lincan/src/ems_cpcpci.c

   1 /* ems_cpcpci.c - support for EMS-WUENSCHE CPC-PCI card
   2  * Linux CAN-bus device driver.
   3  * The card support added by Paolo Grisleri <grisleri@ce.unipr.it>
   4  * This software is released under the GPL-License.
   5  * Version lincan-0.3  17 Jun 2004
   6  */
   7
   8 #include "../include/can.h"
   9 #include "../include/can_sysdep.h"
  10 #include "../include/main.h"
  11 #include "../include/sja1000p.h"
  12
  13 #ifdef CAN_ENABLE_PCI_SUPPORT
  14
  15
  16 /* the only one supported: EMS CPC-PCI */
  17 // PGX: check identifiers name
  18 # define EMS_CPCPCI_PCICAN_VENDOR 0x110a
  19 # define EMS_CPCPCI_PCICAN_ID 0x2104
  20
  21 /*The Infineon PSB4610 PITA-2 is used as PCI to local bus bridge*/
  22 /*BAR0 - MEM - bridge control registers*/
  23
  24 /*BAR1 - MEM - parallel interface*/
  25 /* 0 more EMS control registers
  26  * 0x400 the first SJA1000
  27  * 0x600 the second SJA1000
  28  * each register occupies 4 bytes
  29  */
  30
  31 /*PSB4610 PITA-2 bridge control registers*/
  32 #define PITA2_ICR  0x00  /* Interrupt Control Register */
  33 #define   PITA2_ICR_INT0    0x00000002  /* [RC] INT0 Active/Clear */
  34 #define   PITA2_ICR_GP0_INT 0x00000004  /* [RC] GP0 Interrupt */
  35                                         /* GP0_Int_En=1, GP0_Out_En=0 and low detected */
  36 #define   PITA2_ICR_GP1_INT 0x00000008  /* [RC] GP1 Interrupt */
  37 #define   PITA2_ICR_GP2_INT 0x00000010  /* [RC] GP2 Interrupt */
  38 #define   PITA2_ICR_GP3_INT 0x00000020  /* [RC] GP2 Interrupt */
  39 #define   PITA2_ICR_INT0_En 0x00020000  /* [RW] Enable INT0 */
  40
  41 #define PITA2_MISC 0x1C  /* Miscellaneous Register */
  42 #define   PITA2_MISC_CONFIG 0x04000000
  43                          /* Multiplexed Parallel_interface_mode */
  44
  45 #define EMS_CPCPCI_BYTES_PER_CIRCUIT 0x200
  46 /* Each CPC register occupies 4 bytes */
  47 #define EMS_CPCPCI_BYTES_PER_REG     0x4
  48
  49 // Standard value: Pushpull  (OCTP1|OCTN1|OCTP0|OCTN0|OCM1)
  50 #define EMS_CPCPCI_OCR_DEFAULT_STD 0xDA
  51 // For Galathea piggyback.
  52 #define EMS_CPCPCI_OCR_DEFAULT_GAL 0xDB
  53
  54 /*
  55
  56 The board configuration is probably following:
  57 " RX1 is connected to ground.
  58 " TX1 is not connected.
  59 " CLKO is not connected.
  60 " Setting the OCR register to 0xDA is a good idea.
  61   This means  normal output mode , push-pull and the correct polarity.
  62 " In the CDR register, you should set CBP to 1.
  63   You will probably also want to set the clock divider value to 7
  64   (meaning direct oscillator output) because the second SJA1000 chip
  65   is driven by the first one CLKOUT output.
  66
  67 */
  68
  69
  70
  71 void ems_cpcpci_disconnect_irq(struct candevice_t *candev)
  72 {
  73         /* Disable interrupts from card */
  74         can_writel(0, candev->aux_base_addr + PITA2_ICR);
  75 }
  76
  77 void ems_cpcpci_connect_irq(struct candevice_t *candev)
  78 {
  79         /* Enable interrupts from card */
  80         can_writel(PITA2_ICR_INT0_En, candev->aux_base_addr + PITA2_ICR);
  81 }
  82
  83
  84 int ems_cpcpci_request_io(struct candevice_t *candev)
  85 {
  86         unsigned long pita2_addr;
  87         unsigned long io_addr;
  88         int i;
  89
  90     #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
  91         if(pci_request_region(candev->sysdevptr.pcidev, 0, "ems_cpcpci_pita2") != 0){
  92                 CANMSG("Request of ems_cpcpci_pita2 range failed\n");
  93                 return -ENODEV;
  94         }else if(pci_request_region(candev->sysdevptr.pcidev, 1, "ems_cpcpci_io") != 0){
  95                 CANMSG("Request of ems_cpcpci_io range failed\n");
  96                 goto error_io;
  97         }
  98     #else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
  99         if(pci_request_regions(candev->sysdevptr.pcidev, "EMS_CPCPCI") != 0){
 100                 CANMSG("Request of ems_cpcpci_s5920 regions failed\n");
 101                 return -ENODEV;
 102         }
 103     #endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
 104
 105         pita2_addr=pci_resource_start(candev->sysdevptr.pcidev,0);
 106         if (!(candev->aux_base_addr = ioremap(pita2_addr,
 107               pci_resource_len(candev->sysdevptr.pcidev,0)))) {
 108                 CANMSG("Unable to access I/O memory at: 0x%lx\n", pita2_addr);
 109                 goto error_ioremap_pita2;
 110         }
 111
 112         io_addr=pci_resource_start(candev->sysdevptr.pcidev,1);;
 113         if (!(candev->dev_base_addr = ioremap(io_addr,
 114               pci_resource_len(candev->sysdevptr.pcidev,1)))) {
 115                 CANMSG("Unable to access I/O memory at: 0x%lx\n", io_addr);
 116                 goto error_ioremap_io;
 117         }
 118
 119         candev->io_addr=io_addr;
 120         candev->res_addr=pita2_addr;
 121
 122         /*
 123          * this is redundant with chip initialization, but remap address
 124          * can change when resources are temporarily released
 125          */
 126         for(i=0;i<candev->nr_all_chips;i++) {
 127                 struct canchip_t *chip=candev->chip[i];
 128                 if(!chip) continue;
 129                 chip->chip_base_addr = candev->dev_base_addr+
 130                         0x400 + i*EMS_CPCPCI_BYTES_PER_CIRCUIT;
 131                 if(!chip->msgobj[0]) continue;
 132                 chip->msgobj[0]->obj_base_addr=chip->chip_base_addr;
 133         }
 134
 135         /* Configure PITA-2 parallel interface */
 136         can_writel(PITA2_MISC_CONFIG, candev->aux_base_addr + PITA2_MISC);
 137
 138         ems_cpcpci_disconnect_irq(candev);
 139
 140         return 0;
 141
 142     error_ioremap_io:
 143         iounmap(candev->aux_base_addr);
 144     error_ioremap_pita2:
 145     #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
 146         pci_release_region(candev->sysdevptr.pcidev, 1);
 147     error_io:
 148         pci_release_region(candev->sysdevptr.pcidev, 0);
 149     #else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
 150         pci_release_regions(candev->sysdevptr.pcidev);
 151     #endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
 152
 153         return -ENODEV;
 154 }
 155
 156 int ems_cpcpci_release_io(struct candevice_t *candev)
 157 {
 158         ems_cpcpci_disconnect_irq(candev);
 159
 160         iounmap(candev->dev_base_addr);
 161         iounmap(candev->aux_base_addr);
 162     #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
 163         pci_release_region(candev->sysdevptr.pcidev, 1);
 164         pci_release_region(candev->sysdevptr.pcidev, 0);
 165     #else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
 166         pci_release_regions(candev->sysdevptr.pcidev);
 167     #endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
 168
 169         return 0;
 170 }
 171
 172
 173 void ems_cpcpci_write_register(unsigned data, can_ioptr_t address)
 174 {
 175         address += ((can_ioptr2ulong(address)&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
 176                                              *(EMS_CPCPCI_BYTES_PER_REG-1));
 177         can_writeb(data,address);
 178 }
 179
 180 unsigned ems_cpcpci_read_register(can_ioptr_t address)
 181 {
 182         address += ((can_ioptr2ulong(address)&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
 183                                              *(EMS_CPCPCI_BYTES_PER_REG-1));
 184         return can_readb(address);
 185 }
 186
 187 int ems_cpcpci_irq_handler(int irq, struct canchip_t *chip)
 188 {
 189         //struct canchip_t *chip=(struct canchip_t *)dev_id;
 190         struct candevice_t *candev=chip->hostdevice;
 191         int i;
 192         unsigned long icr;
 193         int test_irq_again;
 194
 195         icr=can_readl(candev->aux_base_addr + PITA2_ICR);
 196         if(!(icr & PITA2_ICR_INT0)) return CANCHIP_IRQ_NONE;
 197
 198         /* correct way to handle interrupts from all chips connected to the one PITA-2 */
 199         do {
 200                 can_writel(PITA2_ICR_INT0_En | PITA2_ICR_INT0, candev->aux_base_addr + PITA2_ICR);
 201                 test_irq_again=0;
 202                 for(i=0;i<candev->nr_all_chips;i++){
 203                         chip=candev->chip[i];
 204                         if(!chip || !(chip->flags&CHIP_CONFIGURED))
 205                                 continue;
 206                         if(sja1000p_irq_handler(irq, chip))
 207                                 test_irq_again=1;
 208                 }
 209                 icr=can_readl(candev->aux_base_addr + PITA2_ICR);
 210         } while((icr & PITA2_ICR_INT0)||test_irq_again);
 211         return CANCHIP_IRQ_HANDLED;
 212 }
 213
 214 int ems_cpcpci_reset(struct candevice_t *candev)
 215 {
 216         int i=0,chip_nr;
 217         struct canchip_t *chip;
 218         unsigned cdr;
 219
 220         DEBUGMSG("Resetting EMS_CPCPCI hardware ...\n");
 221
 222         /* Assert PTADR# - we're in passive mode so the other bits are not important */
 223
 224         ems_cpcpci_disconnect_irq(candev);
 225
 226         for(chip_nr=0;chip_nr<candev->nr_all_chips;chip_nr++){
 227                 if(!candev->chip[chip_nr]) continue;
 228                 chip=candev->chip[chip_nr];
 229
 230                 ems_cpcpci_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
 231                 udelay(1000);
 232
 233                 cdr=ems_cpcpci_read_register(chip->chip_base_addr+SJACDR);
 234                 ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
 235
 236                 ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER);
 237
 238                 i=20;
 239                 ems_cpcpci_write_register(0, chip->chip_base_addr+SJAMOD);
 240                 while (ems_cpcpci_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
 241                         if(!i--) return -ENODEV;
 242                         udelay(1000);
 243                         ems_cpcpci_write_register(0, chip->chip_base_addr+SJAMOD);
 244                 }
 245
 246                 cdr=ems_cpcpci_read_register(chip->chip_base_addr+SJACDR);
 247                 ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
 248
 249                 ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER);
 250
 251                 ems_cpcpci_read_register(chip->chip_base_addr+SJAIR);
 252         }
 253
 254
 255         ems_cpcpci_connect_irq(candev);
 256
 257         return 0;
 258 }
 259
 260 int ems_cpcpci_init_hw_data(struct candevice_t *candev)
 261 {
 262         struct pci_dev *pcidev = NULL;
 263         int i;
 264         unsigned long l;
 265
 266         pcidev = pci_find_device(EMS_CPCPCI_PCICAN_VENDOR, EMS_CPCPCI_PCICAN_ID, pcidev);
 267         if(pcidev == NULL) return -ENODEV;
 268
 269         if (pci_enable_device (pcidev)){
 270                 printk(KERN_CRIT "Setup of EMS_CPCPCI failed\n");
 271                 return -EIO;
 272         }
 273         candev->sysdevptr.pcidev=pcidev;
 274
 275         for(i=0;i<2;i++){
 276                 if(!(pci_resource_flags(pcidev,0)&IORESOURCE_MEM)){
 277                         printk(KERN_CRIT "EMS_CPCPCI region %d is not memory\n",i);
 278                         return -EIO;
 279                 }
 280         }
 281
 282         /*request IO access temporarily to check card presence*/
 283         if(ems_cpcpci_request_io(candev)<0)
 284                 return -ENODEV;
 285
 286         /*** candev->aux_base_addr=pci_resource_start(pcidev,0); ***/
 287         /* some control registers */
 288         /*** candev->dev_base_addr=pci_resource_start(pcidev,1); ***/
 289         /* 0 more EMS control registers
 290          * 0x400 the first SJA1000
 291          * 0x600 the second SJA1000
 292          * each register occupies 4 bytes
 293          */
 294
 295         /*candev->flags |= CANDEV_PROGRAMMABLE_IRQ;*/
 296
 297         for(l=0,i=0;i<4;i++){
 298                 l<<=8;
 299                 l|=can_readb(candev->dev_base_addr + i*4);
 300         }
 301         i=can_readb(candev->dev_base_addr + i*5);
 302
 303         CANMSG("EMS CPC-PCI check value %04lx, ID %d\n", l, i);
 304
 305         if(l!=0x55aa01cb) {
 306                 CANMSG("EMS CPC-PCI unexpected check values\n");
 307         }
 308
 309         /*if (!strcmp(candev->hwname,"ems_cpcpci"))*/
 310         candev->nr_82527_chips=0;
 311         candev->nr_sja1000_chips=2;
 312         candev->nr_all_chips=2;
 313
 314         ems_cpcpci_release_io(candev);
 315
 316         return 0;
 317 }
 318
 319 int ems_cpcpci_init_chip_data(struct candevice_t *candev, int chipnr)
 320 {
 321         if(candev->sysdevptr.pcidev==NULL)
 322                 return -ENODEV;
 323
 324         /* initialize common routines for the SJA1000 chip */
 325         sja1000p_fill_chipspecops(candev->chip[chipnr]);
 326
 327         /* special version of the IRQ handler is required for CPC-PCI board */
 328         candev->chip[chipnr]->chipspecops->irq_handler=ems_cpcpci_irq_handler;
 329
 330         candev->chip[chipnr]->chip_irq=candev->sysdevptr.pcidev->irq;
 331
 332         candev->chip[chipnr]->chip_base_addr = candev->dev_base_addr+
 333                         0x400 + chipnr*EMS_CPCPCI_BYTES_PER_CIRCUIT;
 334         candev->chip[chipnr]->flags = 0;
 335         candev->chip[chipnr]->int_cpu_reg = 0;
 336         candev->chip[chipnr]->int_clk_reg = 0;
 337         candev->chip[chipnr]->int_bus_reg = 0;
 338         /* CLKOUT has to be equal to oscillator frequency to drive second chip */
 339         candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | 7;
 340         candev->chip[chipnr]->sja_ocr_reg = EMS_CPCPCI_OCR_DEFAULT_STD;
 341         candev->chip[chipnr]->clock = 16000000;
 342         candev->chip[chipnr]->flags |= CHIP_IRQ_PCI;
 343
 344         return 0;
 345 }
 346
 347 int ems_cpcpci_init_obj_data(struct canchip_t *chip, int objnr)
 348 {
 349         chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
 350         return 0;
 351 }
 352
 353 int ems_cpcpci_program_irq(struct candevice_t *candev)
 354 {
 355
 356         return 0;
 357 }
 358
 359 int ems_cpcpci_register(struct hwspecops_t *hwspecops)
 360 {
 361         hwspecops->request_io = ems_cpcpci_request_io;
 362         hwspecops->release_io = ems_cpcpci_release_io;
 363         hwspecops->reset = ems_cpcpci_reset;
 364         hwspecops->init_hw_data = ems_cpcpci_init_hw_data;
 365         hwspecops->init_chip_data = ems_cpcpci_init_chip_data;
 366         hwspecops->init_obj_data = ems_cpcpci_init_obj_data;
 367         hwspecops->write_register = ems_cpcpci_write_register;
 368         hwspecops->read_register = ems_cpcpci_read_register;
 369         hwspecops->program_irq = ems_cpcpci_program_irq;
 370         return 0;
 371 }
 372
 373
 374 #endif /*CAN_ENABLE_PCI_SUPPORT*/