1 /******************************************************************************
3 * $RCSfile: lpcVIC.h,v $
6 * Header file for Philips LPC ARM Processors.
7 * Copyright 2004 R O SoftWare
9 * No guarantees, warrantees, or promises, implied or otherwise.
10 * May be used for hobby or commercial purposes provided copyright
11 * notice remains intact.
13 *****************************************************************************/
17 // Vectored Interrupt Controller Registers (VIC)
20 REG32 irqStatus; // IRQ Status Register
21 REG32 fiqStatus; // FIQ Status Register
22 REG32 rawIntr; // Raw Interrupt Status Register
23 REG32 intSelect; // Interrupt Select Register
24 REG32 intEnable; // Interrupt Enable Register
25 REG32 intEnClear; // Interrupt Enable Clear Register
26 REG32 softInt; // Software Interrupt Register
27 REG32 softIntClear; // Software Interrupt Clear Register
28 REG32 protection; // Protection Enable Register
30 REG32 vectAddr; // Vector Address Register
31 REG32 defVectAddr; // Default Vector Address Register
33 REG32 vectAddr0; // Vector Address 0 Register
34 REG32 vectAddr1; // Vector Address 1 Register
35 REG32 vectAddr2; // Vector Address 2 Register
36 REG32 vectAddr3; // Vector Address 3 Register
37 REG32 vectAddr4; // Vector Address 4 Register
38 REG32 vectAddr5; // Vector Address 5 Register
39 REG32 vectAddr6; // Vector Address 6 Register
40 REG32 vectAddr7; // Vector Address 7 Register
41 REG32 vectAddr8; // Vector Address 8 Register
42 REG32 vectAddr9; // Vector Address 9 Register
43 REG32 vectAddr10; // Vector Address 10 Register
44 REG32 vectAddr11; // Vector Address 11 Register
45 REG32 vectAddr12; // Vector Address 12 Register
46 REG32 vectAddr13; // Vector Address 13 Register
47 REG32 vectAddr14; // Vector Address 14 Register
48 REG32 vectAddr15; // Vector Address 15 Register
50 REG32 vectCntl0; // Vector Control 0 Register
51 REG32 vectCntl1; // Vector Control 1 Register
52 REG32 vectCntl2; // Vector Control 2 Register
53 REG32 vectCntl3; // Vector Control 3 Register
54 REG32 vectCntl4; // Vector Control 4 Register
55 REG32 vectCntl5; // Vector Control 5 Register
56 REG32 vectCntl6; // Vector Control 6 Register
57 REG32 vectCntl7; // Vector Control 7 Register
58 REG32 vectCntl8; // Vector Control 8 Register
59 REG32 vectCntl9; // Vector Control 9 Register
60 REG32 vectCntl10; // Vector Control 10 Register
61 REG32 vectCntl11; // Vector Control 11 Register
62 REG32 vectCntl12; // Vector Control 12 Register
63 REG32 vectCntl13; // Vector Control 13 Register
64 REG32 vectCntl14; // Vector Control 14 Register
65 REG32 vectCntl15; // Vector Control 15 Register
68 // VIC Channel Assignments
88 // Vector Control Register bit definitions
89 #define VIC_ENABLE (1 << 5)
91 // Convert Channel Number to Bit Value
92 #define VIC_BIT(chan) (1 << (chan))