lincan/src/pccan.c

   1 /* pccan.c
   2  * Linux CAN-bus device driver.
   3  * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
   4  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
   5  * email:pisa@cmp.felk.cvut.cz
   6  * This software is released under the GPL-License.
   7  * Version lincan-0.3  17 Jun 2004
   8  */
   9
  10 #include "../include/can.h"
  11 #include "../include/can_sysdep.h"
  12 #include "../include/main.h"
  13 #include "../include/pccan.h"
  14 #include "../include/i82527.h"
  15 #include "../include/sja1000.h"
  16
  17 int pccanf_request_io(struct candevice_t *candev)
  18 {
  19         if (!can_request_io_region(candev->io_addr+0x4000,0x20,DEVICE_NAME)) {
  20                 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr+0x4000);
  21                 return -ENODEV;
  22         }
  23         else if (!can_request_io_region(candev->io_addr+0x6000,0x04,DEVICE_NAME)) {
  24                 can_release_io_region(candev->io_addr+0x4000,0x20);
  25                 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr+0x6000);
  26                 return -ENODEV;
  27         }
  28         else {
  29                 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr+0x4000, candev->io_addr+0x4000+0x20-1);
  30                 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr+0x6000, candev->io_addr+0x6000+0x04-1);
  31         }
  32         return 0;
  33 }
  34
  35 int pccand_request_io(struct candevice_t *candev)
  36 {
  37         if (pccanf_request_io(candev))
  38                 return -ENODEV;
  39
  40         if (!can_request_io_region(candev->io_addr+0x5000,0x20,DEVICE_NAME)) {
  41                 pccanf_release_io(candev);
  42                 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr+0x5000);
  43                 return -ENODEV;
  44         }
  45         else {
  46                 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr+0x5000, candev->io_addr+0x5000+0x20-1);
  47         }
  48         return 0;
  49 }
  50
  51 int pccanq_request_io(struct candevice_t *candev)
  52 {
  53         unsigned long io_addr;
  54         int i;
  55
  56         if (pccand_request_io(candev))
  57                 return -ENODEV;
  58
  59         for(i=0, io_addr=candev->io_addr+0x2000; i<8; i++, io_addr+=0x400) {
  60                 if (!can_request_io_region(io_addr,0x40,DEVICE_NAME)) {
  61                         CANMSG("Unable to open port: 0x%lx\n",io_addr);
  62                         while(i--){
  63                                 io_addr-=0x400;
  64                                 can_release_io_region(io_addr,0x40);
  65                         }
  66                         pccand_release_io(candev);
  67                         return -ENODEV;
  68                 }
  69                 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr, io_addr+0x40-1);
  70         }
  71         return 0;
  72 }
  73
  74 int pccanf_release_io(struct candevice_t *candev)
  75 {
  76         can_release_io_region(candev->io_addr+0x4000,0x20);
  77         can_release_io_region(candev->io_addr+0x6000,0x04);
  78
  79         return 0;
  80 }
  81
  82 int pccand_release_io(struct candevice_t *candev)
  83 {
  84         pccanf_release_io(candev);
  85         can_release_io_region(candev->io_addr+0x5000,0x20);
  86
  87         return 0;
  88 }
  89
  90 int pccanq_release_io(struct candevice_t *candev)
  91 {
  92         unsigned long io_addr;
  93         int i;
  94
  95         pccand_release_io(candev);
  96
  97         for(i=0, io_addr=candev->io_addr+0x2000; i<8; i++, io_addr+=0x400) {
  98                 can_release_io_region(io_addr,0x40);
  99         }
 100
 101         return 0;
 102 }
 103
 104 int pccanf_reset(struct candevice_t *candev)
 105 {
 106         int i=0;
 107
 108         DEBUGMSG("Resetting pccanf/s hardware ...\n");
 109         while (i < 1000000) {
 110                 i++;
 111                 outb(0x00,candev->res_addr);
 112         }
 113         outb(0x01,candev->res_addr);
 114         outb(0x00,candev->chip[0]->chip_base_addr+SJACR);
 115
 116         /* Check hardware reset status */
 117         i=0;
 118         while ( (inb(candev->chip[0]->chip_base_addr+SJACR) & sjaCR_RR)
 119                                                                  && (i<=15) ) {
 120                 udelay(20000);
 121                 i++;
 122         }
 123         if (i>=15) {
 124                 CANMSG("Reset status timeout!\n");
 125                 CANMSG("Please check your hardware.\n");
 126                 return -ENODEV;
 127         }
 128         else
 129                 DEBUGMSG("Chip[0] reset status ok.\n");
 130
 131         return 0;
 132 }
 133
 134 int pccand_reset(struct candevice_t *candev)
 135 {
 136         int i=0,chip_nr=0;
 137
 138         DEBUGMSG("Resetting pccan-d hardware ...\n");
 139         while (i < 1000000) {
 140                 i++;
 141                 outb(0x00,candev->res_addr);
 142         }
 143         outb(0x01,candev->res_addr);
 144         outb(0x00,candev->chip[0]->chip_base_addr+SJACR);
 145         outb(0x00,candev->chip[1]->chip_base_addr+SJACR);
 146
 147         /* Check hardware reset status */
 148         i=0;
 149         for (chip_nr=0; chip_nr<2; chip_nr++) {
 150                 i=0;
 151                 while ( (inb(candev->chip[chip_nr]->chip_base_addr +
 152                                                 SJACR) & sjaCR_RR) && (i<=15) ) {
 153                         udelay(20000);
 154                         i++;
 155                 }
 156                 if (i>=15) {
 157                         CANMSG("Reset status timeout!\n");
 158                         CANMSG("Please check your hardware.\n");
 159                         return -ENODEV;
 160                 }
 161                 else
 162                         DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
 163         }
 164         return 0;
 165 }
 166
 167 int pccanq_reset(struct candevice_t *candev)
 168 {
 169         int i=0,chip_nr=0;
 170
 171         for (i=0; i<4; i++)
 172                 can_disable_irq(candev->chip[i]->chip_irq);
 173
 174         DEBUGMSG("Resetting pccan-q hardware ...\n");
 175         while (i < 100000) {
 176                 i++;
 177                 outb(0x00,candev->res_addr);
 178         }
 179         outb_p(0x01,candev->res_addr);
 180
 181         outb(0x00,candev->chip[2]->chip_base_addr+SJACR);
 182         outb(0x00,candev->chip[3]->chip_base_addr+SJACR);
 183
 184         /* Check hardware reset status */
 185         for (chip_nr=0; chip_nr<2; chip_nr++) {
 186                 i=0;
 187                 while( (inb(candev->chip[chip_nr]->chip_base_addr +
 188                                                 iCPU) & iCPU_RST) && (i<=15) ) {
 189                         udelay(20000);
 190                         i++;
 191                 }
 192                 if (i>=15) {
 193                         CANMSG("Reset status timeout!\n");
 194                         CANMSG("Please check your hardware.\n");
 195                         return -ENODEV;
 196                 }
 197                 else
 198                         DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
 199         }
 200         for (chip_nr=2; chip_nr<4; chip_nr++) {
 201                 i=0;
 202                 while( (inb(candev->chip[chip_nr]->chip_base_addr +
 203                                                 SJACR) & sjaCR_RR) && (i<=15) ) {
 204                         udelay(20000);
 205                         i++;
 206                 }
 207                 if (i>=15) {
 208                         CANMSG("Reset status timeout!\n");
 209                         CANMSG("Please check your hardware.\n");
 210                         return -ENODEV;
 211                 }
 212                 else
 213                         DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
 214         }
 215
 216         for (i=0; i<4; i++)
 217                 can_enable_irq(candev->chip[i]->chip_irq);
 218
 219         return 0;
 220 }
 221
 222 int pccan_init_hw_data(struct candevice_t *candev)
 223 {
 224         candev->res_addr=candev->io_addr+0x6001;
 225         candev->flags |= CANDEV_PROGRAMMABLE_IRQ;
 226
 227         if (!strcmp(candev->hwname,"pccan-q")) {
 228                 candev->nr_82527_chips=2;
 229                 candev->nr_sja1000_chips=2;
 230                 candev->nr_all_chips=4;
 231         }
 232         if (!strcmp(candev->hwname,"pccan-f") |
 233             !strcmp(candev->hwname,"pccan-s")) {
 234                 candev->nr_82527_chips=0;
 235                 candev->nr_sja1000_chips=1;
 236                 candev->nr_all_chips=1;
 237         }
 238         if (!strcmp(candev->hwname,"pccan-d")) {
 239                 candev->nr_82527_chips=0;
 240                 candev->nr_sja1000_chips=2;
 241                 candev->nr_all_chips=2;
 242         }
 243
 244         return 0;
 245 }
 246
 247 int pccan_init_chip_data(struct candevice_t *candev, int chipnr)
 248 {
 249         if (!strcmp(candev->hwname,"pccan-q")) {
 250                 if (chipnr<2) {
 251                         candev->chip[chipnr]->chip_type="i82527";
 252                         candev->chip[chipnr]->flags = CHIP_SEGMENTED;
 253                         candev->chip[chipnr]->int_cpu_reg=iCPU_DSC;
 254                         candev->chip[chipnr]->int_clk_reg=iCLK_SL1;
 255                         candev->chip[chipnr]->int_bus_reg=iBUS_CBY;
 256                         candev->chip[chipnr]->sja_cdr_reg = 0;
 257                         candev->chip[chipnr]->sja_ocr_reg = 0;
 258                 }
 259                 else{
 260                         candev->chip[chipnr]->chip_type="sja1000";
 261                         candev->chip[chipnr]->flags = 0;
 262                         candev->chip[chipnr]->int_cpu_reg = 0;
 263                         candev->chip[chipnr]->int_clk_reg = 0;
 264                         candev->chip[chipnr]->int_bus_reg = 0;
 265                         candev->chip[chipnr]->sja_cdr_reg =
 266                                                                 sjaCDR_CLK_OFF;
 267                         candev->chip[chipnr]->sja_ocr_reg =
 268                                                 sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
 269                 }
 270                 candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x2000+candev->io_addr;
 271         }
 272         else {
 273                 candev->chip[chipnr]->chip_type="sja1000";
 274                 candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x4000+candev->io_addr;
 275                 candev->chip[chipnr]->flags = 0;
 276                 candev->chip[chipnr]->int_cpu_reg = 0;
 277                 candev->chip[chipnr]->int_clk_reg = 0;
 278                 candev->chip[chipnr]->int_bus_reg = 0;
 279                 candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CLK_OFF;
 280                 candev->chip[chipnr]->sja_ocr_reg =
 281                                                 sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
 282         }
 283
 284         candev->chip[chipnr]->clock = 16000000;
 285
 286         return 0;
 287 }
 288
 289 int pccan_init_obj_data(struct chip_t *chip, int objnr)
 290 {
 291         if (!strcmp(chip->chip_type,"sja1000")) {
 292                 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
 293                 }
 294         else {  /* The spacing for this card is 0x3c0 */
 295                 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr+(objnr+1)*0x10+(int)((objnr+1)/4)*0x3c0;
 296                 }
 297
 298         return 0;
 299 }
 300
 301 int pccan_program_irq(struct candevice_t *candev)
 302 {
 303         #define IRQ9 0x01
 304         #define IRQ3 0x02
 305         #define IRQ5 0x03
 306
 307         unsigned char irq_reg_value=0;
 308         int i;
 309
 310         for (i=0; i<4; i++) {
 311                 switch (candev->chip[i]->chip_irq) {
 312                         case 0: {
 313                                 break;
 314                         }
 315                         case 3: {
 316                                 irq_reg_value |= (IRQ3<<(i*2));
 317                                 break;
 318                         }
 319                         case 5: {
 320                                 irq_reg_value |= (IRQ5<<(i*2));
 321                                 break;
 322                         }
 323                         case 9: {
 324                                 irq_reg_value |= (IRQ9<<(i*2));
 325                                 break;
 326                         }
 327                         default: {
 328                                 CANMSG("Supplied interrupt is not supported by the hardware\n");
 329                                 return -ENODEV;
 330                         }
 331                 }
 332         }
 333         outb(irq_reg_value,0x6000+candev->io_addr);
 334         DEBUGMSG("Configured pccan hardware interrupts\n");
 335         outb(0x80,0x6000+candev->io_addr+0x02);
 336         DEBUGMSG("Selected pccan on-board 16 MHz oscillator\n");
 337
 338         return 0;
 339 }
 340
 341 inline void pccan_write_register(unsigned data, unsigned long address)
 342 {
 343         outb(data,address);
 344 }
 345
 346 unsigned pccan_read_register(unsigned long address)
 347 {
 348         return inb(address);
 349 }
 350
 351 int pccanf_register(struct hwspecops_t *hwspecops)
 352 {
 353         hwspecops->request_io = pccanf_request_io;
 354         hwspecops->release_io = pccanf_release_io;
 355         hwspecops->reset = pccanf_reset;
 356         hwspecops->init_hw_data = pccan_init_hw_data;
 357         hwspecops->init_chip_data = pccan_init_chip_data;
 358         hwspecops->init_obj_data = pccan_init_obj_data;
 359         hwspecops->write_register = pccan_write_register;
 360         hwspecops->read_register = pccan_read_register;
 361         hwspecops->program_irq = pccan_program_irq;
 362         return 0;
 363 }
 364
 365
 366 int pccand_register(struct hwspecops_t *hwspecops)
 367 {
 368         hwspecops->request_io = pccand_request_io;
 369         hwspecops->release_io = pccand_release_io;
 370         hwspecops->reset = pccand_reset;
 371         hwspecops->init_hw_data = pccan_init_hw_data;
 372         hwspecops->init_chip_data = pccan_init_chip_data;
 373         hwspecops->init_obj_data = pccan_init_obj_data;
 374         hwspecops->write_register = pccan_write_register;
 375         hwspecops->read_register = pccan_read_register;
 376         hwspecops->program_irq = pccan_program_irq;
 377         return 0;
 378 }
 379
 380
 381 int pccanq_register(struct hwspecops_t *hwspecops)
 382 {
 383         hwspecops->request_io = pccanq_request_io;
 384         hwspecops->release_io = pccanq_release_io;
 385         hwspecops->reset = pccanq_reset;
 386         hwspecops->init_hw_data = pccan_init_hw_data;
 387         hwspecops->init_chip_data = pccan_init_chip_data;
 388         hwspecops->init_obj_data = pccan_init_obj_data;
 389         hwspecops->write_register = pccan_write_register;
 390         hwspecops->read_register = pccan_read_register;
 391         hwspecops->program_irq = pccan_program_irq;
 392         return 0;
 393 }