1 #include "local_config.h"
2 #include <system_def.h>
4 #include <lt_timer_types.h>
5 #include <hal_machperiph.h>
9 #include <lpciap_kvpb.h>
10 #endif /* CONFIG_KEYVAL */
11 #ifdef CONFIG_STDIO_COM_PORT
14 #ifdef CONFIG_OC_UL_DRV_SYSLESS
15 #include <ul_lib/ulan.h>
17 #include <ul_drv_init.h>
18 #include <ul_drv_iac.h>
19 #include <ul_lib/ul_drvdef.h>
20 extern long int uld_jiffies;
21 #endif /* CONFIG_OC_UL_DRV_SYSLESS */
22 #ifdef CONFIG_OC_I2C_DRV_SYSLESS
24 #endif /* CONFIG_OC_I2C_DRV_SYSLESS */
28 volatile lt_ticks_t sys_timer_ticks;
29 void (*timer0_isr_appl_call)(void);
31 #ifdef CONFIG_OC_I2C_DRV_SYSLESS
32 #define I2C_DRV_NA_MSTIMEOUT 10
34 int i2c_drv_na_timer=0;
35 #endif /* CONFIG_OC_I2C_DRV_SYSLESS */
37 static void sysInit(void)
44 // setup the parallel port pin
45 GPIO0->FIOCLR = P0IO_ZERO_BITS; // clear the ZEROs output
46 GPIO0->FIOSET = P0IO_ONE_BITS; // set the ONEs output
47 GPIO0->FIODIR = P0IO_OUTPUT_BITS; // set the output bit direction
49 GPIO1->FIOCLR = P1IO_ZERO_BITS; // clear the ZEROs output
50 GPIO1->FIOSET = P1IO_ONE_BITS; // set the ONEs output
51 GPIO1->FIODIR = P1IO_OUTPUT_BITS; // set the output bit direction
53 GPIO2->FIOCLR = P2IO_ZERO_BITS; // clear the ZEROs output
54 GPIO2->FIOSET = P2IO_ONE_BITS; // set the ONEs output
55 GPIO2->FIODIR = P2IO_OUTPUT_BITS; // set the output bit direction
57 GPIO3->FIOCLR = P3IO_ZERO_BITS; // clear the ZEROs output
58 GPIO3->FIOSET = P3IO_ONE_BITS; // set the ONEs output
59 GPIO3->FIODIR = P3IO_OUTPUT_BITS; // set the output bit direction
61 GPIO4->FIOCLR = P4IO_ZERO_BITS; // clear the ZEROs output
62 GPIO4->FIOSET = P4IO_ONE_BITS; // set the ONEs output
63 GPIO4->FIODIR = P4IO_OUTPUT_BITS; // set the output bit direction
66 IRQ_HANDLER_FNC(timer0_isr)
73 if(timer0_isr_appl_call!=NULL)
74 timer0_isr_appl_call();
75 TIM0->MR0 += PCLK / SYS_TIMER_HZ;
76 TIM0->IR=0x01; // Clear match0 interrupt
77 #ifdef CONFIG_OC_UL_DRV_SYSLESS
80 #ifdef CONFIG_OC_I2C_DRV_SYSLESS
81 if (i2c_drv.flags&I2C_DRV_MS_INPR) {
82 if (i2c_drv.flags&I2C_DRV_NA) {
84 if (i2c_drv_na_timer>I2C_DRV_NA_MSTIMEOUT) {
85 if (i2c_drv.stroke_fnc)
86 i2c_drv.stroke_fnc(&i2c_drv);
92 i2c_drv.flags|=I2C_DRV_NA;
96 } while (((int32_t)(TIM0->MR0-TIM0->TC))<0);
105 request_irq(TIMER0_IRQn, timer0_isr, 0, NULL,NULL);
106 enable_irq(TIMER0_IRQn);
111 TIM0->MR0= PCLK / SYS_TIMER_HZ;
112 TIM0->MCR|=1; /* TMCR_MR0_I; */
114 TIM0->TCR = 1; /* Run timer 0*/
117 #ifdef CONFIG_STDIO_COM_PORT
119 int uartcon_write(int file, const char * ptr, int len)
123 for(cnt=0;cnt<len;cnt++,ptr++){
132 void init_system_stub(void) {
133 system_stub_ops.write=uartcon_write;
136 #endif /* CONFIG_STDIO_COM_PORT */
138 #ifdef CONFIG_OC_UL_DRV_SYSLESS
140 extern unsigned uld_debug_flg; /* Left application set defaults */
142 #ifndef CONFIG_KEYVAL
143 unsigned long lpciap_buff[ISP_RAM2FLASH_BLOCK_SIZE/4];
144 #endif /* CONFIG_KEYVAL */
146 #define UL_MTYPE_START32BIT 0x100
148 static inline int ul_iac_mem_head_rd(uint8_t *buf, int len,
149 uint32_t* pmtype, uint32_t* pstart, uint32_t* plen)
152 if (len<6) return -1;
153 mtype=*(buf++); /* memory type */
155 val=*(buf++); /* start address */
157 if(mtype&UL_MTYPE_START32BIT){
158 if (len<8) return -1;
159 val+=(uint32_t)*(buf++)<<16;
160 val+=(uint32_t)*(buf++)<<24;
163 val=*(buf++); /* length */
165 if(mtype&UL_MTYPE_START32BIT){
167 val+=(uint32_t)*(buf++)<<16;
168 val+=(uint32_t)*(buf++)<<24;
172 mtype&=~UL_MTYPE_START32BIT; /* 32-bit start address */
177 int ul_iac_call_rdm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
179 uint32_t mtype,start,len;
183 if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len))
184 return UL_IAC_RC_PROC;
188 data->buff=(char*)start;
189 return UL_IAC_RC_FREEMSG;
191 return UL_IAC_RC_PROC;
194 int ul_iac_call_erm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
196 uint32_t mtype,start,len;
200 if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len))
201 return UL_IAC_RC_PROC;
205 lpcisp_erase((void*)start,len);
207 return UL_IAC_RC_FREEMSG;
209 #endif /* CONFIG_KEYVAL */
210 return UL_IAC_RC_PROC;
213 int ul_iac_call_wrm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
215 uint32_t mtype,start,len;
219 if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len))
220 return UL_IAC_RC_PROC;
223 memcpy((void*)start,data->buff,data->len);
224 return UL_IAC_RC_FREEMSG;
228 lpcisp_write((char*)start, data->buff, ISP_RAM2FLASH_BLOCK_SIZE);
229 return UL_IAC_RC_FREEMSG;
231 #endif /* CONFIG_KEYVAL */
232 return UL_IAC_RC_PROC;
236 int ul_iac_call_deb(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
238 uint32_t debcmd,mtype,start;
239 uint8_t *p=(uint8_t*)ibuff;
241 if (msginfo->len<1) return UL_IAC_RC_PROC;
244 case 0x10: /* goto */
246 if (msginfo->len<5) return UL_IAC_RC_PROC;
251 if(mtype&UL_MTYPE_START32BIT){
252 mtype&=~UL_MTYPE_START32BIT;
253 if (msginfo->len<7) return UL_IAC_RC_PROC;
254 start+=(uint32_t)*(p++)<<16;
255 start+=(uint32_t)*(p++)<<24;
258 ((void (*)())start)();
261 return UL_IAC_RC_PROC;
264 int ul_iac_call_res(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
266 uint32_t rescmd,pass;
267 uint8_t *p=(uint8_t*)ibuff;
269 if (msginfo->len<1) return UL_IAC_RC_PROC;
272 case ULRES_CPU: /* CPU */
274 if (msginfo->len<3) return UL_IAC_RC_PROC;
278 // MEMMAP=MEMMAP_FLASH;
279 lpc_watchdog_init(1,10); /* 10ms */
285 return UL_IAC_RC_PROC;
291 unsigned int pinsel1_mask = 0;
292 unsigned int pinsel1_set = 0;
293 unsigned int pinsel4_mask = 0;
294 unsigned int pinsel4_set = 0;
296 /* set rs485 mode for UART1 */
297 #if TXD1_BIT == BIT(15)
298 PINCON->PINSEL0 = (PINCON->PINSEL0 & ~0xC0000000) | 0x40000000; /* rxd on P0.15 */
299 #elif TXD1_BIT == BIT(0)
300 pinsel4_mask |= 3 << (0*2);
301 pinsel4_set |= 2 << (0*2);
303 #error TXD1_BIT is not set or valid
306 #if RXD1_BIT == BIT(16)
307 pinsel1_mask |= 3 << ((16-16)*2);
308 pinsel1_set |= 1 << ((16-16)*2);
309 #elif RXD1_BIT == BIT(1)
310 pinsel4_mask |= 3 << (1*2);
311 pinsel4_set |= 2 << (1*2);
313 #error RXD1_BIT is not set or valid
317 #if CTS1_BIT == BIT(17)
318 pinsel1_mask |= 3 << ((17-16)*2);
319 pinsel1_set |= 1 << ((17-16)*2);
320 #elif CTS1_BIT == BIT(2)
321 pinsel4_mask |= 3 << (2*2);
322 pinsel4_set |= 2 << (2*2);
324 #error CTS1_BIT is not valid
329 #if DSR1_BIT == BIT(19)
330 pinsel1_mask |= 3 << ((19-16)*2);
331 pinsel1_set |= 1 << ((19-16)*2);
332 #elif DSR1_BIT == BIT(4)
333 pinsel4_mask |= 3 << (4*2);
334 pinsel4_set |= 2 << (4*2);
336 #error CTS1_BIT is not valid
340 #if RTS1_BIT == BIT(22)
341 pinsel1_mask |= 3 << ((22-16)*2);
342 pinsel1_set |= 1 << ((22-16)*2);
343 #elif RTS1_BIT == BIT(7)
344 pinsel4_mask |= 3 << (7*2);
345 pinsel4_set |= 2 << (7*2);
347 #error RTS1_BIT is not set or valid
350 /* port 0 .. 0x00003000; 0x00001000; rts(uDIR) */
351 PINCON->PINSEL1 = (PINCON->PINSEL1 & ~pinsel1_mask) | pinsel1_set;
352 /* port 2 .. 0x00000C0F; 0x0000080A; dsr(rxd), rxd, txd */
353 PINCON->PINSEL4 = (PINCON->PINSEL4 & ~pinsel4_mask) | pinsel4_set;
355 udrv=ul_drv_new(UL_DRV_SYSLESS_PORT, /* port */
356 UL_DRV_SYSLESS_IRQ, /* irq */
357 UL_DRV_SYSLESS_BAUD, /* baud */
358 UL_DRV_SYSLESS_MY_ADR_DEFAULT, /* my adr */
359 #ifdef CONFIG_OC_UL_DRV_U450_VARPINS
360 #if defined(CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG) && defined(CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP)
361 "16450-dirneg-msrswap", /* chip name */
362 #elif defined(CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP)
363 "16450-msrswap", /* chip name */
364 #elif defined(CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG)
365 "16450-dirneg", /* chip name */
367 "16450", /* chip name */
369 #else /*CONFIG_OC_UL_DRV_U450_VARPINS*/
370 "16450", /* chip name */
371 #endif /*CONFIG_OC_UL_DRV_U450_VARPINS*/
372 0); /* baud base - default */
377 ul_drv_add_iac(udrv,UL_CMD_RDM,UL_IAC_OP_SND,ul_iac_call_rdm,NULL,0,0,NULL,0);
378 ul_drv_add_iac(udrv,UL_CMD_ERM,UL_IAC_OP_CALLBACK,ul_iac_call_erm,NULL,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
379 ul_drv_add_iac(udrv,UL_CMD_WRM,UL_IAC_OP_REC,ul_iac_call_wrm,(char*)lpciap_buff,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
380 ul_drv_add_iac(udrv,UL_CMD_DEB,UL_IAC_OP_CALLBACK,ul_iac_call_deb,NULL,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
381 ul_drv_add_iac(udrv,UL_CMD_RES,UL_IAC_OP_CALLBACK,ul_iac_call_res,NULL,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
383 return ul_drv_add_dev(udrv);
385 #endif /* CONFIG_OC_UL_DRV_SYSLESS */
387 #ifdef CONFIG_OC_I2C_DRV_SYSLESS
392 #if I2C_DRV_SYSLESS_PORT == I2C0_BASE
393 SC->PCONP |= (1 << 7); /*PI2C0*/
394 /* SDA0 P0.27, SCL0 P0.28 */
395 PINCON->PINSEL1 = (PINCON->PINSEL0 & ~0x03c00000) | 0x01400000;
397 #elif I2C_DRV_SYSLESS_PORT == I2C1_BASE
398 SC->PCONP |= (1 << 19); /*PI2C1*/
399 #if SCL1_BIT == BIT(1)
400 /* SDA1 P0.0, SCL1 P0.1 */
401 PINCON->PINSEL0 |= 0x0000000f;
402 PINCON->PINMODE0 = (PINCON->PINMODE0 & ~0x0000000f) | 0x0000000A;
403 PINCON->PINMODE_OD0 |= 0x00000003;
404 #elif SCL1_BIT == BIT(20)
405 /* SDA1 P0.19, SCL1 P0.20 */
406 PINCON->PINSEL1 |= 0x000003c0;
407 PINCON->PINMODE1 = (PINCON->PINMODE1 & ~0x000003c0) | 0x00000280;
408 PINCON->PINMODE_OD0 |= 0x00180000;
410 #error Unknown SCL1_BIT pin position
413 #elif I2C_DRV_SYSLESS_PORT == I2C2_BASE
414 SC->PCONP |= (1 << 26); /*PI2C2*/
415 /* SDA2 P0.10, SCL2 P0.11 */
416 PINCON->PINSEL0 = (PINCON->PINSEL0 & ~0x00f00000) | 0x00A00000;
417 PINCON->PINMODE0 = (PINCON->PINMODE0 & ~0x00f00000) | 0x00A00000;
418 PINCON->PINMODE_OD0 |= 0x00000c00;
420 #error unknown I2C_DRV_SYSLESS_PORT address
423 if (i2c_drv_init(&i2c_drv,
424 I2C_DRV_SYSLESS_PORT,
426 I2C_DRV_SYSLESS_BITRATE,
427 I2C_DRV_SYSLESS_SLADR)<0) return -1;
432 #endif /*CONFIG_OC_I2C_DRV_SYSLESS*/
438 // initialize the system
441 #ifdef WATCHDOG_ENABLED
442 lpc_watchdog_init(1,WATCHDOG_TIMEOUT_MS);
444 #endif /* WATCHDOG_ENABLED */
446 #ifdef CONFIG_STDIO_COM_PORT
447 uart0Init( B57600 , UART_8N1, UART_FIFO_8);
449 #endif /* CONFIG_STDIO_COM_PORT */
451 // initialize the system timer
454 #ifdef CONFIG_OC_UL_DRV_SYSLESS
455 // uld_debug_flg=0x3ff;
457 #endif /* CONFIG_OC_UL_DRV_SYSLESS */
459 #ifdef CONFIG_OC_I2C_DRV_SYSLESS
461 #endif /* CONFIG_OC_I2C_DRV_SYSLESS */