1 /*******************************************************************
2 Components for embedded applications builded for
3 laboratory and medical instruments firmware
5 system_def.h - common cover for definition of hardware adresses,
6 registers, timing and other hardware dependant
7 parts of embedded hardware
9 Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
10 (C) 2002 by PiKRON Ltd. http://www.pikron.com
12 *******************************************************************/
14 #ifndef _SYSTEM_DEF_H_
15 #define _SYSTEM_DEF_H_
18 #include <system_stub.h>
30 #define VER_CODE(major,minor,patch) (major*0x10000+minor*0x100+patch)
31 /* Software version */
32 #define SW_VER_ID "MPX-UU-PC"
33 #define SW_VER_MAJOR 0
34 #define SW_VER_MINOR 2
35 #define SW_VER_PATCH 0
36 #define SW_VER_CODE VER_CODE(SW_VER_MAJOR,SW_VER_MINOR,SW_VER_PATCH)
37 /* Hardware version */
38 #define HW_VER_ID "MPX-UU-PC"
39 #define HW_VER_MAJOR 1
40 #define HW_VER_MINOR 0
41 #define HW_VER_PATCH 0
42 #define HW_VER_CODE VER_CODE(HW_VER_MAJOR,HW_VER_MINOR,HW_VER_PATCH)
43 /* Version of mechanical */
44 #define MECH_VER_ID "MPX-UU-PC"
45 #define MECH_VER_MAJOR 0
46 #define MECH_VER_MINOR 0
47 #define MECH_VER_PATCH 0
48 #define MECH_VER_CODE VER_CODE(MECH_VER_MAJOR,MECH_VER_MINOR,MECH_VER_PATCH)
51 /*--------------------- Clock Configuration ----------------------------------
53 // <e> Clock Configuration
54 // <h> System Controls and Status Register (SCS)
55 // <o1.4> OSCRANGE: Main Oscillator Range Select
56 // <0=> 1 MHz to 20 MHz
57 // <1=> 15 MHz to 24 MHz
58 // <e1.5> OSCEN: Main Oscillator Enable
62 // <h> Clock Source Select Register (CLKSRCSEL)
63 // <o2.0..1> CLKSRC: PLL Clock Source Selection
64 // <0=> Internal RC oscillator
65 // <1=> Main oscillator
66 // <2=> RTC oscillator
69 // <e3> PLL0 Configuration (Main PLL)
70 // <h> PLL0 Configuration Register (PLL0CFG)
71 // <i> F_cco0 = (2 * M * F_in) / N
72 // <i> F_in must be in the range of 32 kHz to 50 MHz
73 // <i> F_cco0 must be in the range of 275 MHz to 550 MHz
74 // <o4.0..14> MSEL: PLL Multiplier Selection
77 // <o4.16..23> NSEL: PLL Divider Selection
83 // <e5> PLL1 Configuration (USB PLL)
84 // <h> PLL1 Configuration Register (PLL1CFG)
85 // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
86 // <i> F_cco1 = F_osc * M * 2 * P
87 // <i> F_cco1 must be in the range of 156 MHz to 320 MHz
88 // <o6.0..4> MSEL: PLL Multiplier Selection
90 // <i> M Value (for USB maximum value is 4)
91 // <o6.5..6> PSEL: PLL Divider Selection
100 // <h> CPU Clock Configuration Register (CCLKCFG)
101 // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
105 // <h> USB Clock Configuration Register (USBCLKCFG)
106 // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL1
108 // <i> Divide is USBSEL + 1
111 // <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
112 // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
113 // <0=> Pclk = Cclk / 4
115 // <2=> Pclk = Cclk / 2
116 // <3=> Pclk = Hclk / 8
117 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
118 // <0=> Pclk = Cclk / 4
120 // <2=> Pclk = Cclk / 2
121 // <3=> Pclk = Hclk / 8
122 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
123 // <0=> Pclk = Cclk / 4
125 // <2=> Pclk = Cclk / 2
126 // <3=> Pclk = Hclk / 8
127 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
128 // <0=> Pclk = Cclk / 4
130 // <2=> Pclk = Cclk / 2
131 // <3=> Pclk = Hclk / 8
132 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
133 // <0=> Pclk = Cclk / 4
135 // <2=> Pclk = Cclk / 2
136 // <3=> Pclk = Hclk / 8
137 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
138 // <0=> Pclk = Cclk / 4
140 // <2=> Pclk = Cclk / 2
141 // <3=> Pclk = Hclk / 8
142 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
143 // <0=> Pclk = Cclk / 4
145 // <2=> Pclk = Cclk / 2
146 // <3=> Pclk = Hclk / 8
147 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
148 // <0=> Pclk = Cclk / 4
150 // <2=> Pclk = Cclk / 2
151 // <3=> Pclk = Hclk / 8
152 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
153 // <0=> Pclk = Cclk / 4
155 // <2=> Pclk = Cclk / 2
156 // <3=> Pclk = Hclk / 8
157 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
158 // <0=> Pclk = Cclk / 4
160 // <2=> Pclk = Cclk / 2
161 // <3=> Pclk = Hclk / 8
162 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
163 // <0=> Pclk = Cclk / 4
165 // <2=> Pclk = Cclk / 2
166 // <3=> Pclk = Hclk / 8
167 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
168 // <0=> Pclk = Cclk / 4
170 // <2=> Pclk = Cclk / 2
171 // <3=> Pclk = Hclk / 6
172 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
173 // <0=> Pclk = Cclk / 4
175 // <2=> Pclk = Cclk / 2
176 // <3=> Pclk = Hclk / 6
177 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
178 // <0=> Pclk = Cclk / 4
180 // <2=> Pclk = Cclk / 2
181 // <3=> Pclk = Hclk / 6
184 // <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
185 // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
186 // <0=> Pclk = Cclk / 4
188 // <2=> Pclk = Cclk / 2
189 // <3=> Pclk = Hclk / 8
190 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
191 // <0=> Pclk = Cclk / 4
193 // <2=> Pclk = Cclk / 2
194 // <3=> Pclk = Hclk / 8
195 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
196 // <0=> Pclk = Cclk / 4
198 // <2=> Pclk = Cclk / 2
199 // <3=> Pclk = Hclk / 8
200 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
201 // <0=> Pclk = Cclk / 4
203 // <2=> Pclk = Cclk / 2
204 // <3=> Pclk = Hclk / 8
205 // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
206 // <0=> Pclk = Cclk / 4
208 // <2=> Pclk = Cclk / 2
209 // <3=> Pclk = Hclk / 8
210 // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
211 // <0=> Pclk = Cclk / 4
213 // <2=> Pclk = Cclk / 2
214 // <3=> Pclk = Hclk / 8
215 // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
216 // <0=> Pclk = Cclk / 4
218 // <2=> Pclk = Cclk / 2
219 // <3=> Pclk = Hclk / 8
220 // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
221 // <0=> Pclk = Cclk / 4
223 // <2=> Pclk = Cclk / 2
224 // <3=> Pclk = Hclk / 8
225 // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
226 // <0=> Pclk = Cclk / 4
228 // <2=> Pclk = Cclk / 2
229 // <3=> Pclk = Hclk / 8
230 // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
231 // <0=> Pclk = Cclk / 4
233 // <2=> Pclk = Cclk / 2
234 // <3=> Pclk = Hclk / 8
235 // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
236 // <0=> Pclk = Cclk / 4
238 // <2=> Pclk = Cclk / 2
239 // <3=> Pclk = Hclk / 8
240 // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
241 // <0=> Pclk = Cclk / 4
243 // <2=> Pclk = Cclk / 2
244 // <3=> Pclk = Hclk / 8
245 // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
246 // <0=> Pclk = Cclk / 4
248 // <2=> Pclk = Cclk / 2
249 // <3=> Pclk = Hclk / 8
250 // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
251 // <0=> Pclk = Cclk / 4
253 // <2=> Pclk = Cclk / 2
254 // <3=> Pclk = Hclk / 8
257 // <h> Power Control for Peripherals Register (PCONP)
258 // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
259 // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
260 // <o11.3> PCUART0: UART 0 power/clock enable
261 // <o11.4> PCUART1: UART 1 power/clock enable
262 // <o11.6> PCPWM1: PWM 1 power/clock enable
263 // <o11.7> PCI2C0: I2C interface 0 power/clock enable
264 // <o11.8> PCSPI: SPI interface power/clock enable
265 // <o11.9> PCRTC: RTC power/clock enable
266 // <o11.10> PCSSP1: SSP interface 1 power/clock enable
267 // <o11.12> PCAD: A/D converter power/clock enable
268 // <o11.13> PCCAN1: CAN controller 1 power/clock enable
269 // <o11.14> PCCAN2: CAN controller 2 power/clock enable
270 // <o11.15> PCGPIO: GPIOs power/clock enable
271 // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
272 // <o11.17> PCMC: Motor control PWM power/clock enable
273 // <o11.18> PCQEI: Quadrature encoder interface power/clock enable
274 // <o11.19> PCI2C1: I2C interface 1 power/clock enable
275 // <o11.21> PCSSP0: SSP interface 0 power/clock enable
276 // <o11.22> PCTIM2: Timer 2 power/clock enable
277 // <o11.23> PCTIM3: Timer 3 power/clock enable
278 // <o11.24> PCUART2: UART 2 power/clock enable
279 // <o11.25> PCUART3: UART 3 power/clock enable
280 // <o11.26> PCI2C2: I2C interface 2 power/clock enable
281 // <o11.27> PCI2S: I2S interface power/clock enable
282 // <o11.29> PCGPDMA: GP DMA function power/clock enable
283 // <o11.30> PCENET: Ethernet block power/clock enable
284 // <o11.31> PCUSB: USB interface power/clock enable
289 #define CLOCK_SETUP 1
291 #define SCS_Val 0x00000020 /* OSCEN */
292 #define CLKSRCSEL_Val 0x00000001 /* XTAL */
295 #define PLL0CFG_Val 0x0000000B /* 324403200Hz - must be in the range 275HMz-550MHz */
298 #define PLL1CFG_Val 0x00000023
300 #define CCLKCFG_Val 0x00000003 /* pplclk/(CCLKCFG_Val+1)=81100800Hz */
301 #define USBCLKCFG_Val 0x00000005
303 //#define PCLKSEL0_Val 0x00000000 /* all peripherial sysclk/4 */
304 //#define PCLKSEL1_Val 0x00000000
305 //#define PCONP_Val 0x042887DE
307 #define PCONP_CLK_DIV(x) ((x)==0?4:((x)==1?1:((x)==2?2:8)))
309 /*--------------------- Flash Accelerator Configuration ----------------------
311 // <e> Flash Accelerator Configuration
312 // <o1.0..1> FETCHCFG: Fetch Configuration
313 // <0=> Instruction fetches from flash are not buffered
314 // <1=> One buffer is used for all instruction fetch buffering
315 // <2=> All buffers may be used for instruction fetch buffering
316 // <3=> Reserved (do not use this setting)
317 // <o1.2..3> DATACFG: Data Configuration
318 // <0=> Data accesses from flash are not buffered
319 // <1=> One buffer is used for all data access buffering
320 // <2=> All buffers may be used for data access buffering
321 // <3=> Reserved (do not use this setting)
322 // <o1.4> ACCEL: Acceleration Enable
323 // <o1.5> PREFEN: Prefetch Enable
324 // <o1.6> PREFOVR: Prefetch Override
325 // <o1.12..15> FLASHTIM: Flash Access Time
326 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
327 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
328 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
329 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
330 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
331 // <5=> 6 CPU clocks (for any CPU clock)
334 #define FLASH_SETUP 1
335 #define FLASHCFG_Val 0x0000403A
337 /*----------------------------------------------------------------------------
339 *----------------------------------------------------------------------------*/
340 #define XTAL (12000000UL) /* Oscillator frequency */
341 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
342 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
343 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
348 #define SYS_TIMER_HZ 1000
351 #define BIT(n) (1 << (n))
354 // Port Bit Definitions & Macros: Description - initial conditions
355 #define P0_0_UNUSED_BIT BIT(0) // P0.0 unused - low output
356 #define P0_1_UNUSED_BIT BIT(1) // P0.1 unused - low output
357 #define TXD0_BIT BIT(2) // used by UART0
358 #define RXD0_BIT BIT(3) // used by UART0
359 #define P0_6_UNUSED_BIT BIT(6) // P0.6 unused - low output
360 #define P0_7_UNUSED_BIT BIT(7) // P0.7 unused - low output
361 #define P0_8_UNUSED_BIT BIT(8) // P0.8 unused - low output
362 #define P0_9_UNUSED_BIT BIT(9) // P0.9 unused - low output
363 #define P0_10_UNUSED_BIT BIT(10) // P0.10 unused - low output
364 #define P0_11_UNUSED_BIT BIT(11) // P0.11 unused - low output
365 #define P0_15_UNUSED_BIT BIT(15) // P0.15 unused - low output
366 #define P0_16_UNUSED_BIT BIT(16) // P0.16 unused - low output
367 #define LED1_BIT BIT(17) // P0.17 LED1
368 #define LED2_BIT BIT(18) // P0.18 LED2
369 #define P0_22_UNUSED_BIT BIT(22) // P0.22 unused - low output
370 #define P0_25_UNUSED_BIT BIT(25) // P0.25 unused - low output
371 #define P0_26_UNUSED_BIT BIT(26) // P0.26 unused - low output
372 #define USBDPLUS_BIT BIT(29) // P0.29 USBD+
373 #define USBDMINUS_BIT BIT(30) // P0.30 USBD-
376 // Port Bit Definitions & Macros: Description - initial conditions
377 #define P1_0_UNUSED_BIT BIT(0) // P1.0 unused - low output
378 #define P1_1_UNUSED_BIT BIT(1) // P1.1 unused - low output
379 #define P1_4_UNUSED_BIT BIT(4) // P1.4 unused - low output
380 #define P1_8_UNUSED_BIT BIT(8) // P1.8 unused - low output
381 #define P1_9_UNUSED_BIT BIT(9) // P1.9 unused - low output
382 #define P1_10_UNUSED_BIT BIT(10) // P1.10 unused - low output
383 #define P1_14_UNUSED_BIT BIT(14) // P1.14 unused - low output
384 #define P1_15_UNUSED_BIT BIT(15) // P1.15 unused - low output
385 #define P1_18_UNUSED_BIT BIT(18) // P1.18 unused - low output
386 #define WDT_BIT BIT(19) // P1.19 WDT
387 #define P1_20_UNUSED_BIT BIT(20) // P1.20 unused - low output
388 #define P1_22_UNUSED_BIT BIT(22) // P1.22 unused - low output
389 #define P1_23_UNUSED_BIT BIT(23) // P1.23 unused - low output
390 #define P1_24_UNUSED_BIT BIT(24) // P1.24 unused - low output
391 #define P1_25_UNUSED_BIT BIT(25) // P1.25 unused - low output
392 #define P1_26_UNUSED_BIT BIT(26) // P1.26 unused - low output
393 #define P1_28_UNUSED_BIT BIT(28) // P1.28 unused - low output
394 #define P1_29_UNUSED_BIT BIT(29) // P1.29 unused - low output
395 #define VBUS_BIT BIT(30) // P1.30
396 #define P1_31_UNUSED_BIT BIT(31) // P1.31 unused - low output
398 // Port Bit Definitions & Macros: Description - initial conditions
399 #define TXD1_BIT BIT(0) // P2.0 TXD
400 #define RXD1_BIT BIT(1) // P2.1 RXD
401 #define CTS1_BIT BIT(2) // P2.2 CTS connected to RXD1
402 #define P2_3_UNUSED_BIT BIT(3) // P2.3 unused - low output
403 #define DSR1_BIT BIT(4) // P2.4 DSR connected to TXD1
404 #define P2_5_UNUSED_BIT BIT(5) // P2.5 unused - low output
405 #define P2_6_UNUSED_BIT BIT(6) // P2.6 unused - low output
406 #define RTS1_BIT BIT(7) // P2.7 RTS1 used as DIR1
407 #define P2_8_UNUSED_BIT BIT(8) // P2.8 unused - low output
408 #define USB_CONNECT_BIT BIT(9) // P2.9 USB output for soft connect
409 #define BOOT_BIT BIT(10) // P2.10 Boot input
411 #define P4_28_UNUSED_BIT BIT(28) // P4.28 unused - low output
412 #define P4_29_UNUSED_BIT BIT(29) // P4.29 unused - low output
414 #define P0IO_INPUT_BITS (uint32_t) ( \
420 #define P1IO_INPUT_BITS (uint32_t) ( \
424 #define P2IO_INPUT_BITS (uint32_t) ( \
431 #define P3IO_INPUT_BITS (uint32_t) ( \
434 #define P4IO_INPUT_BITS (uint32_t) ( \
437 #define P0IO_ZERO_BITS (uint32_t) ( \
453 #define P1IO_ZERO_BITS (uint32_t) ( \
474 #define P2IO_ZERO_BITS (uint32_t) ( \
481 #define P3IO_ZERO_BITS (uint32_t) ( \
484 #define P4IO_ZERO_BITS (uint32_t) ( \
489 #define P0IO_ONE_BITS (uint32_t) ( \
495 #define P1IO_ONE_BITS (uint32_t) ( \
499 #define P2IO_ONE_BITS (uint32_t) ( \
505 #define P3IO_ONE_BITS (uint32_t) ( \
508 #define P4IO_ONE_BITS (uint32_t) ( \
511 #define P0IO_OUTPUT_BITS (uint32_t) ( \
515 #define P1IO_OUTPUT_BITS (uint32_t) ( \
519 #define P2IO_OUTPUT_BITS (uint32_t) ( \
523 #define P3IO_OUTPUT_BITS (uint32_t) ( \
527 #define P4IO_OUTPUT_BITS (uint32_t) ( \
533 /***************************************************************************/
535 #define LED_GP LED1_BIT /* GENREAL PURPOSE LED */
536 #define LED_ERR LED2_BIT
538 /***************************************************************************/
540 #define LED_PORT GPIO0->FIO
541 #define OUT_PORT GPIO1->FIO
543 #define CREATE_PORT_NAME_PIN(port) port##PIN
544 #define CREATE_PORT_NAME_CLR(port) port##CLR
545 #define CREATE_PORT_NAME_SET(port) port##SET
547 #define GET_IN_PIN(port,in) ((CREATE_PORT_NAME_PIN(port) & in)?1:0)
548 #define GET_IN_PORT(port) (CREATE_PORT_NAME_PIN(port))
549 #define SET_OUT_PIN(port,out) (CREATE_PORT_NAME_SET(port)=out)
550 #define CLR_OUT_PIN(port,out) (CREATE_PORT_NAME_CLR(port)=out)
552 /***************************************************************************/
554 #define WATCHDOG_ENABLED
555 #define WATCHDOG_TIMEOUT_MS 1000
557 /***************************************************************************/
558 /* uLan configuration */
564 #ifdef ULD_DEFAULT_BUFFER_SIZE
565 #undef ULD_DEFAULT_BUFFER_SIZE
566 #define ULD_DEFAULT_BUFFER_SIZE 0x2000
569 #define UL_DRV_SYSLESS_PORT UART1_BASE
570 #define UL_DRV_SYSLESS_BAUD 19200
571 #define UL_DRV_SYSLESS_IRQ UART1_IRQn
572 #define UL_DRV_SYSLESS_MY_ADR_DEFAULT 1
574 #define watchdog_feed lpc_watchdog_feed
575 #define kvpb_erase lpcisp_kvpb_erase
576 #define kvpb_copy lpcisp_kvpb_copy
577 #define kvpb_flush lpcisp_kvpb_flush
578 #define KVPB_DEFAULT_FLAGS KVPB_DESC_DOUBLE|KVPB_DESC_CHUNKWO
580 /***************************************************************************/
581 /* USB configuration */
582 #define USB_WITH_UDEV_FNC
583 #define USB_EP_NUM 32
584 #define USB_MAX_PACKET0 64
585 #define USB_MAX_PACKET 8
586 #define USB_DMA_EP 0x00000000
588 #define USB_VBUS_PIN_USED 1
591 #endif /* _SYSTEM_DEF_H_ */