1 /******************************************************************************
6 * Header file for Philips LPC17xx USB enabled ARM Processors
7 * Copyright 2006-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz>
8 * Based on same author code for LPC214x
10 * No guarantees, warrantees, or promises, implied or otherwise.
11 * May be used for hobby or commercial purposes provided copyright
12 * notice remains intact or GPL license is applied.
14 *****************************************************************************/
19 #if !defined(REG_8) || !defined(REG16) || !defined(REG32)
20 #define REG_8 volatile unsigned char
21 #define REG16 volatile unsigned short
22 #define REG32 volatile unsigned long
25 /* USBIntSt - USB Interrupt Status (R/W) */
26 #define USB_INT_REQ_LP (1<<0) /*Low priority interrupt line status (RO) */
27 #define USB_INT_REQ_HP (1<<1) /*High priority interrupt line status. (RO) */
28 #define USB_INT_REQ_DMA (1<<2) /*DMA interrupt line status. This bit is read only. (LPC2146/8 only) */
29 #define USB_need_clock (1<<8) /*USB need clock indicator*/
30 #define USB_EN_USB_INTS (1<<31) /*Enable all USB interrupts*/
32 /* USB Host Controller Registers */
33 #define HcControlHeadED_o 0x0020 /* PADDR of 1st EP desc. of control list (R/W) */
34 #define HcControlCurrentED_o 0x0024 /* PADDR of curr. EP desc. of control list (R/W) */
35 #define HcBulkHeadED_o 0x0028 /* PADDR of 1st EP desc. of bulk list (R/W) */
36 #define HcBulkCurrentED_o 0x002C /* PADDR of curr. EP desc. of bulk list (R/W) */
37 #define HcDoneHead_o 0x0030 /* PADDR of the last desct added to Done q. (R) */
38 #define HcFmInterval_o 0x0034 /* full speed max frame time (R/W) */
39 #define HcFmRemaining_o 0x0038 /* 14-bit counter of remaining in curr. frame (R) */
40 #define HcFmNumber_o 0x003C /* 16-bit HC and HDC timing counter (R) */
41 #define HcPeriodicStart_o 0x0040 /* 14-bit earliest time to start HC periodic list (R/W) */
42 #define HcLSThreshold_o 0x0044 /* 11-bit HC timer for 8-byte LS packet before EOF (R/W) */
43 #define HcRhDescriptorA_o 0x0048 /* Characteristics of the root hub - 1st part (R/W) */
44 #define HcRhDescriptorB_o 0x004C /* Characteristics of the root hub - 2nd part (R/W) */
45 #define HcRhStatus_o 0x0050 /* D-word hub info (low - status, high change) (R/W) */
46 #define USB_MODULE_ID_o 0x00FC /* USB Module ID 0x3505yyzz - yy .. ver, zz .. rev (R) */
48 /* USB On-The-Go Registers */
49 #define OTGIntSt_o 0x0100 /* OTG Interrupt Status (RO) */
50 #define OTGIntEn_o 0x0104 /* OTG Interrupt Enable (R/W) */
51 #define OTGIntSet_o 0x0108 /* OTG Interrupt Clear (WO) */
52 #define OTGIntClr_o 0x010C /* OTG Interrupt Clear (WO) */
53 #define OTGStCtrl_o 0x0110 /* OTG Status and Control (R/W) */
54 #define OTGTmr_o 0x0114 /* OTG Timer (R/W) */
56 /* Device interrupt registers */
57 #define USBDevIntSt_o 0x0200 /* USB Device Interrupt Status(R0) */
58 #define USBDevIntEn_o 0x0204 /* USB Device Interrupt Enable (R/W) */
59 #define USBDevIntClr_o 0x0208 /* USB Device Interrupt Clear (WO) */
60 #define USBDevIntSet_o 0x020C /* USB Device Interrupt Set (WO) */
61 #define USBDevInt_FRAME (1<<0) /*Frame interrupt @1kHz for ISO transfers*/
62 #define USBDevInt_EP_FAST (1<<1) /*Fast interrupt transfer for the endpoint*/
63 #define USBDevInt_EP_SLOW (1<<2) /*Slow interrupt transfer for the endpoint*/
64 #define USBDevInt_DEV_STAT (1<<3) /*USB Bus reset, USB suspend change or Connect occured*/
65 #define USBDevInt_CCEMTY (1<<4) /*Command code register is empty/ready for CMD*/
66 #define USBDevInt_CDFULL (1<<5) /*Command data register is full/data available*/
67 #define USBDevInt_RxENDPKT (1<<6) /*Current packet in the FIFO is transferred to the CPU*/
68 #define USBDevInt_TxENDPKT (1<<7) /*TxPacket bytes written to FIFO*/
69 #define USBDevInt_EP_RLZED (1<<8) /*Endpoints realized after Maxpacket size update*/
70 #define USBDevInt_ERR_INT (1<<9) /*Error Interrupt - Use Read Error Status Command 0xFB*/
71 #define USBDevIntPri_o 0x022C /* USB Device Interrupt Priority (WO) */
72 #define USBDevIntPri_FRAME (1<<0) /*0/1 FRAME int routed to the low/high priority interrupt line*/
73 #define USBDevIntPri_EP_FAST (1<<1) /*0/1 EP_FAST int routed to the low/high priority line*/
75 /* Endpoint interrupt registers - bits corresponds to EP0 to EP31 */
76 #define USBEpIntSt_o 0x0230 /* USB Endpoint Interrupt Status (R0) */
77 #define USBEpIntEn_o 0x0234 /* USB Endpoint Interrupt Enable (R/W) */
78 #define USBEpIntClr_o 0x0238 /* USB Endpoint Interrupt Clear (WO) */
79 #define USBEpIntSet_o 0x023C /* USB Endpoint Interrupt Set (WO) */
80 #define USBEpIntPri_o 0x0240 /* USB Endpoint Interrupt Priority (WO) */
81 /* Endpoint realization registers */
82 #define USBReEp_o 0x0244 /* USB Realize Endpoint (R/W) */
83 #define USBEpInd_o 0x0248 /* USB Endpoint Index (RO) */
84 #define USBEpInd_Ind 0x001F /* Index for subsequent USBMaxPSize (WO) */
85 #define USBMaxPSize_o 0x024C /* USB MaxPacketSize (R/W) */
86 #define USBMaxPSize_Size 0x03FF /* The maximum packet size value */
87 /* USB transfer registers */
88 #define USBRxData_o 0x0218 /* USB Receive Data (RO) */
89 #define USBRxPLen_o 0x0220 /* USB Receive Packet Length (RO) */
90 #define USBRxPLen_PKT_LNGTH (0x03FF) /*Remaining amount of bytes to be read from RAM*/
91 #define USBRxPLen_DV (1<<10) /*Data valid. 0 only for error ISO packet*/
92 #define USBRxPLen_PKT_RDY (1<<11) /*Packet length valid and packet is ready for reading*/
93 #define USBTxData_o 0x021C /* USB Transmit Data (WO) */
94 #define USBTxPLen_o 0x0224 /* USB Transmit Packet Length (WO) */
95 #define USBTxPLen_PKT_LNGTH (0x03FF) /*Remaining amount of bytes to be written to the EP_RAM*/
96 #define USBCtrl_o 0x0228 /* USB Control (R/W) */
97 #define USBCtrl_RD_EN (1<<0) /*Read mode control*/
98 #define USBCtrl_WR_EN (1<<1) /*Write mode control*/
99 #define USBCtrl_LOG_ENDPOINT 0x003C /*Logical Endpoint number*/
100 /* Command registers */
101 #define USBCmdCode_o 0x0210 /* USB Command Code (WO) */
102 #define USBCmdCode_CMD_PHASE 0x0000FF00 /*The command phase*/
103 #define USBCmdCode_CMD_CODE 0x00FF0000 /*The code for the command*/
104 #define USBCmdData_o 0x0214 /* USB Command Data (RO) */
105 /* DMA registers (LPC2146/8 and LPC17xx only) */
106 #define USBDMARSt_o 0x0250 /* USB DMA Request Status (RO) */
107 #define USBDMARClr_o 0x0254 /* USB DMA Request Clear (WO) */
108 #define USBDMARSet_o 0x0258 /* USB DMA Request Set (WO) */
109 #define USBUDCAH_o 0x0280 /* USB UDCA Head (R/W) has to be aligned to 128 bytes */
110 #define USBEpDMASt_o 0x0284 /* USB Endpoint DMA Status (RO) */
111 #define USBEpDMAEn_o 0x0288 /* USB Endpoint DMA Enable (WO) */
112 #define USBEpDMADis_o 0x028C /* USB Endpoint DMA Disable (WO) */
113 #define USBDMAIntSt_o 0x0290 /* USB DMA Interrupt Status (RO) */
114 #define USBDMAIntEn_o 0x0294 /* USB DMA Interrupt Enable (R/W) */
115 #define USBDMAInt_EoT (1<<0) /*End of Transfer Interrupt bit, 1 if USBEoTIntSt != 0*/
116 #define USBDMAInt_New_DD_Rq (1<<1) /* New DD Request Interrupt bit, 1 if USBNDDRIntSt != 0*/
117 #define USBDMAInt_SysError (1<<2) /*System Error Interrupt bit, 1 if USBSysErrIntSt != 0*/
118 #define USBEoTIntSt_o 0x02A0 /* USB End of Transfer Interrupt Status (RO) */
119 #define USBEoTIntClr_o 0x02A4 /* USB End of Transfer Interrupt Clear (WO) */
120 #define USBEoTIntSet_o 0x02A8 /* USB End of Transfer Interrupt Set (WO) */
121 #define USBNDDRIntSt_o 0x02AC /* USB New DD Request Interrupt Status (RO) */
122 #define USBNDDRIntClr_o 0x02B0 /* USB New DD Request Interrupt Clear (WO) */
123 #define USBNDDRIntSet_o 0x02B4 /* USB New DD Request Interrupt Set (WO) */
124 #define USBSysErrIntSt_o 0x02B8 /* USB System Error Interrupt Status (RO) */
125 #define USBSysErrIntClr_o 0x02BC /* USB System Error Interrupt Clear (WO) */
126 #define USBSysErrIntSet_o 0x02C0 /* USB System Error Interrupt Set (WO) */
128 /* USB I2C registers */
129 #define USB_I2C_RX_o 0x0300 /* I2C Receive (RO) */
130 #define USB_I2C_TX_o 0x0300 /* I2C Transmit (WO) */
131 #define USB_I2C_STS_o 0x0304 /* I2C Status (RO) */
132 #define USB_I2C_CTL_o 0x0308 /* I2C Control (R/W) */
133 #define USB_I2C_CLKHI_o 0x030C /* I2C Clock High (R/W) */
134 #define USB_I2C_CLKLO_o 0x0310 /* I2C Clock Low (WO) */
136 /* Clock control registers */
137 #define OTGClkCtrl_o 0x0FF4 /* OTG Clock Control (R/W) */
138 #define USBClkCtrl_o 0x0FF4 /* USB Clock Control (R/W) */
139 #define OTGClkSt_o 0x0FF8 /* OTG Clock Status (RO) */
140 #define USBClkSt_o 0x0FF8 /* USB Clock Status (RO) */
143 #define USB_CMD_SET_ADDR 0x00D00500
144 #define USB_CMD_CFG_DEV 0x00D80500
145 #define USB_CMD_SET_MODE 0x00F30500
146 #define USB_CMD_RD_FRAME 0x00F50500
147 #define USB_DAT_RD_FRAME 0x00F50200
148 #define USB_CMD_RD_TEST 0x00FD0500
149 #define USB_DAT_RD_TEST 0x00FD0200
150 #define USB_CMD_SET_DEV_STAT 0x00FE0500
151 #define USB_CMD_GET_DEV_STAT 0x00FE0500
152 #define USB_DAT_GET_DEV_STAT 0x00FE0200
153 #define USB_CMD_GET_ERR_CODE 0x00FF0500
154 #define USB_DAT_GET_ERR_CODE 0x00FF0200
155 #define USB_CMD_RD_ERR_STAT 0x00FB0500
156 #define USB_DAT_RD_ERR_STAT 0x00FB0200
157 #define USB_DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
158 #define USB_CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
159 #define USB_DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
160 #define USB_CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
161 #define USB_DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
162 #define USB_CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
163 #define USB_CMD_CLR_BUF 0x00F20500
164 #define USB_DAT_CLR_BUF 0x00F20200
165 #define USB_CMD_VALID_BUF 0x00FA0500
167 /* Device Address Register Definitions */
168 #define USBC_DEV_ADDR_MASK 0x7F
169 #define USBC_DEV_EN 0x80
171 /* Device Configure Register Definitions */
172 #define USBC_CONF_DEVICE 0x01
174 /* Device Mode Register Definitions */
175 #define USBC_AP_CLK 0x01
176 #define USBC_INAK_CI 0x02
177 #define USBC_INAK_CO 0x04
178 #define USBC_INAK_II 0x08
179 #define USBC_INAK_IO 0x10
180 #define USBC_INAK_BI 0x20
181 #define USBC_INAK_BO 0x40
183 /* Device Status Register Definitions */
184 #define USBC_DEV_CON 0x01
185 #define USBC_DEV_CON_CH 0x02
186 #define USBC_DEV_SUS 0x04
187 #define USBC_DEV_SUS_CH 0x08
188 #define USBC_DEV_RST 0x10
190 /* Error Code Register Definitions */
191 #define USBC_ERR_EC_MASK 0x0F
192 #define USBC_ERR_EA 0x10
194 /* Error Status Register Definitions */
195 #define USBC_ERR_PID 0x01
196 #define USBC_ERR_UEPKT 0x02
197 #define USBC_ERR_DCRC 0x04
198 #define USBC_ERR_TIMOUT 0x08
199 #define USBC_ERR_EOP 0x10
200 #define USBC_ERR_B_OVRN 0x20
201 #define USBC_ERR_BTSTF 0x40
202 #define USBC_ERR_TGL 0x80
204 /* Endpoint Select Register Definitions */
205 #define USBC_EP_SEL_F 0x01
206 #define USBC_EP_SEL_ST 0x02
207 #define USBC_EP_SEL_STP 0x04
208 #define USBC_EP_SEL_PO 0x08
209 #define USBC_EP_SEL_EPN 0x10
210 #define USBC_EP_SEL_B_1_FULL 0x20
211 #define USBC_EP_SEL_B_2_FULL 0x40
213 /* Endpoint Status Register Definitions */
214 #define USBC_EP_STAT_ST 0x01
215 #define USBC_EP_STAT_DA 0x20
216 #define USBC_EP_STAT_RF_MO 0x40
217 #define USBC_EP_STAT_CND_ST 0x80
219 /* Clear Buffer Register Definitions */
220 #define USBC_CLR_BUF_PO 0x01
225 /* Device interrupt registers */
226 REG32 DevIntSt; /* USB Device Interrupt Status (RO) 0000 */
227 REG32 DevIntEn; /* USB Device Interrupt Enable (R/W) 0004 */
228 REG32 DevIntClr; /* USB Device Interrupt Clear (WO) 0008 */
229 REG32 DevIntSet; /* USB Device Interrupt Set (WO) 000C */
230 /* Command registers */
231 REG32 CmdCode; /* USB Command Code (WO) 0010 */
232 REG32 CmdData; /* USB Command Data (RO) 0014 */
233 /* USB transfer registers */
234 REG32 RxData; /* USB Receive Data (RO) 0018 */
235 REG32 TxData; /* USB Transmit Data (WO) 001C */
236 REG32 RxPLen; /* USB Receive Packet Length (RO) 0020 */
237 REG32 TxPLen; /* USB Transmit Packet Length (WO) 0024 */
238 REG32 Ctrl; /* USB Control (R/W) 0028 */
239 /* Device interrupt priority register */
240 REG_8 USBDevIntPri; /* USB Device Interrupt Priority (WO) 002C */
242 /* Endpoint interrupt registers */
243 REG32 EpIntSt; /* USB Endpoint Interrupt Status (RO) 0030 */
244 REG32 EpIntEn; /* USB Endpoint Interrupt Enable (R/W) 0034 */
245 REG32 EpIntClr; /* USB Endpoint Interrupt Clear (WO) 0038 */
246 REG32 EpIntSet; /* USB Endpoint Interrupt Set (WO) 003C */
247 REG32 EpIntPri; /* USB Endpoint Priority (WO) 0040 */
248 /* Endpoint realization registers */
249 REG32 ReEp; /* USB Realize Endpoint (R/W) 0044 */
250 REG32 EpInd; /* USB Endpoint Index (WO) 0048 */
251 REG32 MaxPSize; /* USB MaxPacketSize (R/W) 004C */
252 /* DMA registers (LPC2146/8 only) */
253 REG32 DMARSt; /* USB DMA Request Status (RO) 0050 */
254 REG32 DMARClr; /* USB DMA Request Clear (WO) 0054 */
255 REG32 DMARSet; /* USB DMA Request Set (WO) 0058 */
257 REG32 UDCAH; /* USB UDCA Head (R/W) 0080 */
258 REG32 EpDMASt; /* USB Endpoint DMA Status (RO) 0084 */
259 REG32 EpDMAEn; /* USB Endpoint DMA Enable (WO) 0088 */
260 REG32 EpDMADis; /* USB Endpoint DMA Disable (WO) 008C */
261 REG32 DMAIntSt; /* USB DMA Interrupt Status (RO) 0090 */
262 REG32 DMAIntEn; /* USB DMA Interrupt Enable (R/W) 0094 */
264 REG32 EoTIntSt; /* USB End of Transfer Interrupt Status (RO) 00A0 */
265 REG32 EoTIntClr; /* USB End of Transfer Interrupt Clear (WO) 00A4 */
266 REG32 EoTIntSet; /* USB End of Transfer Interrupt Set (WO) 00A8 */
267 REG32 NDDRIntSt; /* USB New DD Request Interrupt Status (RO) 00AC */
268 REG32 NDDRIntClr; /* USB New DD Request Interrupt Clear (WO) 00B0 */
269 REG32 NDDRIntSet; /* USB New DD Request Interrupt Set (WO) 00B4 */
270 REG32 SysErrIntSt; /* USB System Error Interrupt Status (RO) 00B8 */
271 REG32 SysErrIntClr; /* USB System Error Interrupt Clear (WO) 00BC */
272 REG32 SysErrIntSet; /* USB System Error Interrupt Set (WO) 00C0 */
275 #define USBIntSt (*(REG32*)0x400FC10) /* USB Interrupt Status (R/W) */
277 #define USB_REGS_BASE 0x5000C000UL
279 #define HcControlHeadED_o 0x0020 /* PADDR of 1st EP desc. of control list (R/W) */
280 #define HcControlCurrentED_o 0x0024 /* PADDR of curr. EP desc. of control list (R/W) */
281 #define HcBulkHeadED_o 0x0028 /* PADDR of 1st EP desc. of bulk list (R/W) */
282 #define HcBulkCurrentED_o 0x002C /* PADDR of curr. EP desc. of bulk list (R/W) */
283 #define HcDoneHead_o 0x0030 /* PADDR of the last desct added to Done q. (R) */
284 #define HcFmInterval_o 0x0034 /* full speed max frame time (R/W) */
285 #define HcFmRemaining_o 0x0038 /* 14-bit counter of remaining in curr. frame (R) */
286 #define HcFmNumber_o 0x003C /* 16-bit HC and HDC timing counter (R) */
287 #define HcPeriodicStart_o 0x0040 /* 14-bit earliest time to start HC periodic list (R/W) */
288 #define HcLSThreshold_o 0x0044 /* 11-bit HC timer for 8-byte LS packet before EOF (R/W) */
289 #define HcRhDescriptorA_o 0x0048 /* Characteristics of the root hub - 1st part (R/W) */
290 #define HcRhDescriptorB_o 0x004C /* Characteristics of the root hub - 2nd part (R/W) */
291 #define HcRhStatus_o 0x0050 /* D-word hub info (low - status, high change) (R/W) */
293 #define HcControlHeadED (*(REG32*)(USB_REGS_BASE+HcControlHeadED_o))
294 #define HcControlCurrentED (*(REG32*)(USB_REGS_BASE+HcControlCurrentED_o))
295 #define HcBulkHeadED (*(REG32*)(USB_REGS_BASE+HcBulkHeadED_o))
296 #define HcBulkCurrentED (*(REG32*)(USB_REGS_BASE+HcBulkCurrentED_o))
297 #define HcDoneHead (*(REG32*)(USB_REGS_BASE+HcDoneHead_o))
298 #define HcFmInterval (*(REG32*)(USB_REGS_BASE+HcFmInterval_o))
299 #define HcFmRemaining (*(REG32*)(USB_REGS_BASE+HcFmRemaining_o))
300 #define HcFmNumber (*(REG32*)(USB_REGS_BASE+HcFmNumber_o))
301 #define HcPeriodicStart (*(REG32*)(USB_REGS_BASE+HcPeriodicStart_o))
302 #define HcLSThreshold (*(REG32*)(USB_REGS_BASE+HcLSThreshold_o))
303 #define HcRhDescriptorA (*(REG32*)(USB_REGS_BASE+HcRhDescriptorA_o))
304 #define HcRhDescriptorB (*(REG32*)(USB_REGS_BASE+HcRhDescriptorB_o))
305 #define HcRhStatus (*(REG32*)(USB_REGS_BASE+HcRhStatus_o))
307 #define USB_MODULE_ID (*(REG32*)(USB_REGS_BASE+USB_MODULE_ID_o))
309 #define OTGIntSt (*(REG32*)(USB_REGS_BASE+OTGIntSt_o))
310 #define OTGIntEn (*(REG32*)(USB_REGS_BASE+OTGIntEn_o))
311 #define OTGIntClr (*(REG32*)(USB_REGS_BASE+OTGIntClr_o))
312 #define OTGIntSet (*(REG32*)(USB_REGS_BASE+OTGIntSet_o))
313 #define OTGStCtrl (*(REG32*)(USB_REGS_BASE+OTGStCtrl_o))
314 #define OTGTmr (*(REG32*)(USB_REGS_BASE+OTGTmr_o))
316 #define USBDevIntSt (*(REG32*)(USB_REGS_BASE+USBDevIntSt_o))
317 #define USBDevIntEn (*(REG32*)(USB_REGS_BASE+USBDevIntEn_o))
318 #define USBDevIntClr (*(REG32*)(USB_REGS_BASE+USBDevIntClr_o))
319 #define USBDevIntSet (*(REG32*)(USB_REGS_BASE+USBDevIntSet_o))
320 #define USBDevIntPri (*(REG32*)(USB_REGS_BASE+USBDevIntPri_o))
321 #define USBEpIntSt (*(REG32*)(USB_REGS_BASE+USBEpIntSt_o))
322 #define USBEpIntEn (*(REG32*)(USB_REGS_BASE+USBEpIntEn_o))
323 #define USBEpIntClr (*(REG32*)(USB_REGS_BASE+USBEpIntClr_o))
324 #define USBEpIntSet (*(REG32*)(USB_REGS_BASE+USBEpIntSet_o))
325 #define USBEpIntPri (*(REG32*)(USB_REGS_BASE+USBEpIntPri_o))
326 #define USBReEp (*(REG32*)(USB_REGS_BASE+USBReEp_o))
327 #define USBEpInd (*(REG32*)(USB_REGS_BASE+USBEpInd_o))
328 #define USBMaxPSize (*(REG32*)(USB_REGS_BASE+USBMaxPSize_o))
329 #define USBRxData (*(REG32*)(USB_REGS_BASE+USBRxData_o))
330 #define USBRxPLen (*(REG32*)(USB_REGS_BASE+USBRxPLen_o))
331 #define USBTxData (*(REG32*)(USB_REGS_BASE+USBTxData_o))
332 #define USBTxPLen (*(REG32*)(USB_REGS_BASE+USBTxPLen_o))
333 #define USBCtrl (*(REG32*)(USB_REGS_BASE+USBCtrl_o))
334 #define USBCmdCode (*(REG32*)(USB_REGS_BASE+USBCmdCode_o))
335 #define USBCmdData (*(REG32*)(USB_REGS_BASE+USBCmdData_o))
336 #define USBDMARSt (*(REG32*)(USB_REGS_BASE+USBDMARSt_o))
337 #define USBDMARClr (*(REG32*)(USB_REGS_BASE+USBDMARClr_o))
338 #define USBDMARSet (*(REG32*)(USB_REGS_BASE+USBDMARSet_o))
339 #define USBUDCAH (*(REG32*)(USB_REGS_BASE+USBUDCAH_o))
340 #define USBEpDMASt (*(REG32*)(USB_REGS_BASE+USBEpDMASt_o))
341 #define USBEpDMAEn (*(REG32*)(USB_REGS_BASE+USBEpDMAEn_o))
342 #define USBEpDMADis (*(REG32*)(USB_REGS_BASE+USBEpDMADis_o))
343 #define USBDMAIntSt (*(REG32*)(USB_REGS_BASE+USBDMAIntSt_o))
344 #define USBDMAIntEn (*(REG32*)(USB_REGS_BASE+USBDMAIntEn_o))
345 #define USBEoTIntSt (*(REG32*)(USB_REGS_BASE+USBEoTIntSt_o))
346 #define USBEoTIntClr (*(REG32*)(USB_REGS_BASE+USBEoTIntClr_o))
347 #define USBEoTIntSet (*(REG32*)(USB_REGS_BASE+USBEoTIntSet_o))
348 #define USBNDDRIntSt (*(REG32*)(USB_REGS_BASE+USBNDDRIntSt_o))
349 #define USBNDDRIntClr (*(REG32*)(USB_REGS_BASE+USBNDDRIntClr_o))
350 #define USBNDDRIntSet (*(REG32*)(USB_REGS_BASE+USBNDDRIntSet_o))
351 #define USBSysErrIntSt (*(REG32*)(USB_REGS_BASE+USBSysErrIntSt_o))
352 #define USBSysErrIntClr (*(REG32*)(USB_REGS_BASE+USBSysErrIntClr_o))
353 #define USBSysErrIntSet (*(REG32*)(USB_REGS_BASE+USBSysErrIntSet_o))
355 #define USB_I2C_RX (*(REG32*)(USB_REGS_BASE+I2C_RX_o))
356 #define USB_I2C_TX (*(REG32*)(USB_REGS_BASE+I2C_TX_o))
357 #define USB_I2C_STS (*(REG32*)(USB_REGS_BASE+I2C_STS_o))
358 #define USB_I2C_CTL (*(REG32*)(USB_REGS_BASE+I2C_CTL_o))
359 #define USB_I2C_CLKHI (*(REG32*)(USB_REGS_BASE+I2C_CLKHI_o))
360 #define USB_I2C_CLKLO (*(REG32*)(USB_REGS_BASE+I2C_CLKLO_o))
361 #define OTGClkCtrl (*(REG32*)(USB_REGS_BASE+OTGClkCtrl_o))
362 #define USBClkCtrl (*(REG32*)(USB_REGS_BASE+USBClkCtrl_o))
363 #define OTGClkSt (*(REG32*)(USB_REGS_BASE+OTGClkSt_o))
364 #define USBClkSt (*(REG32*)(USB_REGS_BASE+USBClkSt_o))