lincan/src/sja1000p.c

   1 /* sja1000.c
   2  * Linux CAN-bus device driver.
   3  * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
   4  * Changed for PeliCan mode SJA1000 by Tomasz Motylewski (BFAD GmbH)
   5  * T.Motylewski@bfad.de
   6  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
   7  * email:pisa@cmp.felk.cvut.cz
   8  * This software is released under the GPL-License.
   9  * Version lincan-0.3  17 Jun 2004
  10  */
  11
  12 #include "../include/can.h"
  13 #include "../include/can_sysdep.h"
  14 #include "../include/main.h"
  15 #include "../include/sja1000p.h"
  16
  17 #ifdef CONFIG_OC_LINCAN_DETAILED_ERRORS
  18
  19 static const char *sja1000_ecc_errc_str[]={
  20         "bit error",
  21         "form error",
  22         "stuff error",
  23         "other type of error"
  24 };
  25
  26 static const char *sja1000_ecc_seg_str[]={
  27         "?0?",
  28         "?1?",
  29         "ID.28 to ID.21",
  30         "start of frame",
  31         "bit SRTR",
  32         "bit IDE",
  33         "ID.20 to ID.18",
  34         "ID.17 to ID.13",
  35         "CRC sequence",
  36         "reserved bit 0",
  37         "data field",
  38         "data length code",
  39         "bit RTR",
  40         "reserved bit 1",
  41         "ID.4 to ID.0",
  42         "ID.12 to ID.5",
  43         "?16?"
  44         "active error flag",
  45         "intermission",
  46         "tolerate dominant bits",
  47         "?20?",
  48         "?21?",
  49         "passive error flag",
  50         "error delimiter",
  51         "CRC delimiter",
  52         "acknowledge slot",
  53         "end of frame",
  54         "acknowledge delimiter",
  55         "overload flag",
  56         "?29?",
  57         "?30?",
  58         "?31?"
  59 };
  60
  61 #endif /*CONFIG_OC_LINCAN_DETAILED_ERRORS*/
  62
  63 static int sja1000_report_error_limit_counter;
  64
  65 static void sja1000_report_error(struct canchip_t *chip,
  66                                 unsigned sr, unsigned ir, unsigned ecc)
  67 {
  68         if(sja1000_report_error_limit_counter>=100)
  69                 return;
  70
  71         CANMSG("Error: status register: 0x%x irq_register: 0x%02x error: 0x%02x\n",
  72                 sr, ir, ecc);
  73
  74         sja1000_report_error_limit_counter+=10;
  75
  76         if(sja1000_report_error_limit_counter>=100){
  77                 sja1000_report_error_limit_counter+=10;
  78                 CANMSG("Error: too many errors, reporting disabled\n");
  79                 return;
  80         }
  81
  82 #ifdef CONFIG_OC_LINCAN_DETAILED_ERRORS
  83         CANMSG("SR: BS=%c  ES=%c  TS=%c  RS=%c  TCS=%c TBS=%c DOS=%c RBS=%c\n",
  84                 sr&sjaSR_BS?'1':'0',sr&sjaSR_ES?'1':'0',
  85                 sr&sjaSR_TS?'1':'0',sr&sjaSR_RS?'1':'0',
  86                 sr&sjaSR_TCS?'1':'0',sr&sjaSR_TBS?'1':'0',
  87                 sr&sjaSR_DOS?'1':'0',sr&sjaSR_RBS?'1':'0');
  88         CANMSG("IR: BEI=%c ALI=%c EPI=%c WUI=%c DOI=%c EI=%c  TI=%c  RI=%c\n",
  89                 sr&sjaIR_BEI?'1':'0',sr&sjaIR_ALI?'1':'0',
  90                 sr&sjaIR_EPI?'1':'0',sr&sjaIR_WUI?'1':'0',
  91                 sr&sjaIR_DOI?'1':'0',sr&sjaIR_EI?'1':'0',
  92                 sr&sjaIR_TI?'1':'0',sr&sjaIR_RI?'1':'0');
  93         if((sr&sjaIR_EI) || 1){
  94                 CANMSG("EI: %s %s %s\n",
  95                        sja1000_ecc_errc_str[(ecc&(sjaECC_ERCC1|sjaECC_ERCC0))/sjaECC_ERCC0],
  96                        ecc&sjaECC_DIR?"RX":"TX",
  97                        sja1000_ecc_seg_str[ecc&sjaECC_SEG_M]
  98                       );
  99         }
 100 #endif /*CONFIG_OC_LINCAN_DETAILED_ERRORS*/
 101 }
 102
 103
 104 /**
 105  * sja1000p_enable_configuration - enable chip configuration mode
 106  * @chip: pointer to chip state structure
 107  */
 108 int sja1000p_enable_configuration(struct canchip_t *chip)
 109 {
 110         int i=0;
 111         enum sja1000_PeliCAN_MOD flags;
 112
 113         can_disable_irq(chip->chip_irq);
 114
 115         flags=can_read_reg(chip,SJAMOD);
 116
 117         while ((!(flags & sjaMOD_RM)) && (i<=10)) {
 118                 can_write_reg(chip, sjaMOD_RM, SJAMOD);
 119 // TODO: configurable sjaMOD_AFM (32/16 bit acceptance filter)
 120 // config sjaMOD_LOM (listen only)
 121                 udelay(100);
 122                 i++;
 123                 flags=can_read_reg(chip, SJAMOD);
 124         }
 125         if (i>=10) {
 126                 CANMSG("Reset error\n");
 127                 can_enable_irq(chip->chip_irq);
 128                 return -ENODEV;
 129         }
 130
 131         return 0;
 132 }
 133
 134 /**
 135  * sja1000p_disable_configuration - disable chip configuration mode
 136  * @chip: pointer to chip state structure
 137  */
 138 int sja1000p_disable_configuration(struct canchip_t *chip)
 139 {
 140         int i=0;
 141         enum sja1000_PeliCAN_MOD flags;
 142
 143         flags=can_read_reg(chip,SJAMOD);
 144
 145         while ( (flags & sjaMOD_RM) && (i<=50) ) {
 146 // could be as long as 11*128 bit times after buss-off
 147                 can_write_reg(chip, 0, SJAMOD);
 148 // TODO: configurable sjaMOD_AFM (32/16 bit acceptance filter)
 149 // config sjaMOD_LOM (listen only)
 150                 udelay(100);
 151                 i++;
 152                 flags=can_read_reg(chip, SJAMOD);
 153         }
 154         if (i>=10) {
 155                 CANMSG("Error leaving reset status\n");
 156                 return -ENODEV;
 157         }
 158
 159         can_enable_irq(chip->chip_irq);
 160
 161         return 0;
 162 }
 163
 164 /**
 165  * sja1000p_chip_config: - can chip configuration
 166  * @chip: pointer to chip state structure
 167  *
 168  * This function configures chip and prepares it for message
 169  * transmission and reception. The function resets chip,
 170  * resets mask for acceptance of all messages by call to
 171  * sja1000p_extended_mask() function and then
 172  * computes and sets baudrate with use of function sja1000p_baud_rate().
 173  * Return Value: negative value reports error.
 174  * File: src/sja1000p.c
 175  */
 176 int sja1000p_chip_config(struct canchip_t *chip)
 177 {
 178         int i;
 179         unsigned char n, r;
 180
 181         if (sja1000p_enable_configuration(chip))
 182                 return -ENODEV;
 183
 184         /* Set mode, clock out, comparator */
 185         can_write_reg(chip,sjaCDR_PELICAN|chip->sja_cdr_reg,SJACDR);
 186
 187         /* Ensure, that interrupts are disabled even on the chip level now */
 188         can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER);
 189
 190         /* Set driver output configuration */
 191         can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
 192
 193         /* Simple check for chip presence */
 194         for (i=0, n=0x5a; i<8; i++, n+=0xf) {
 195                 can_write_reg(chip,n,SJAACR0+i);
 196         }
 197         for (i=0, n=0x5a; i<8; i++, n+=0xf) {
 198                 r = n^can_read_reg(chip,SJAACR0+i);
 199                 if (r) {
 200                         CANMSG("sja1000p_chip_config: chip connection broken,"
 201                                 " readback differ 0x%02x\n", r);
 202                         return -ENODEV;
 203                 }
 204         }
 205
 206
 207         if (sja1000p_extended_mask(chip,0x00000000, 0xffffffff))
 208                 return -ENODEV;
 209
 210         if (!chip->baudrate)
 211                 chip->baudrate=1000000;
 212         if (sja1000p_baud_rate(chip,chip->baudrate,chip->clock,0,75,0))
 213                 return -ENODEV;
 214
 215         /* Enable hardware interrupts */
 216         can_write_reg(chip, sjaENABLE_INTERRUPTS, SJAIER);
 217
 218         sja1000p_disable_configuration(chip);
 219
 220         return 0;
 221 }
 222
 223 /**
 224  * sja1000p_extended_mask: - setup of extended mask for message filtering
 225  * @chip: pointer to chip state structure
 226  * @code: can message acceptance code
 227  * @mask: can message acceptance mask
 228  *
 229  * Return Value: negative value reports error.
 230  * File: src/sja1000p.c
 231  */
 232 int sja1000p_extended_mask(struct canchip_t *chip, unsigned long code, unsigned  long mask)
 233 {
 234         int i;
 235
 236         if (sja1000p_enable_configuration(chip))
 237                 return -ENODEV;
 238
 239 // LSB to +3, MSB to +0
 240         for(i=SJA_PeliCAN_AC_LEN; --i>=0;) {
 241                 can_write_reg(chip,code&0xff,SJAACR0+i);
 242                 can_write_reg(chip,mask&0xff,SJAAMR0+i);
 243                 code >>= 8;
 244                 mask >>= 8;
 245         }
 246
 247         DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
 248         DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
 249
 250         sja1000p_disable_configuration(chip);
 251
 252         return 0;
 253 }
 254
 255 /**
 256  * sja1000p_baud_rate: - set communication parameters.
 257  * @chip: pointer to chip state structure
 258  * @rate: baud rate in Hz
 259  * @clock: frequency of sja1000 clock in Hz (ISA osc is 14318000)
 260  * @sjw: synchronization jump width (0-3) prescaled clock cycles
 261  * @sampl_pt: sample point in % (0-100) sets (TSEG1+1)/(TSEG1+TSEG2+2) ratio
 262  * @flags: fields %BTR1_SAM, %OCMODE, %OCPOL, %OCTP, %OCTN, %CLK_OFF, %CBP
 263  *
 264  * Return Value: negative value reports error.
 265  * File: src/sja1000p.c
 266  */
 267 int sja1000p_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
 268                                                         int sampl_pt, int flags)
 269 {
 270         int best_error = 1000000000, error;
 271         int best_tseg=0, best_brp=0, best_rate=0, brp=0;
 272         int tseg=0, tseg1=0, tseg2=0;
 273
 274         if (sja1000p_enable_configuration(chip))
 275                 return -ENODEV;
 276
 277         clock /=2;
 278
 279         /* tseg even = round down, odd = round up */
 280         for (tseg=(0+0+2)*2; tseg<=(sjaMAX_TSEG2+sjaMAX_TSEG1+2)*2+1; tseg++) {
 281                 brp = clock/((1+tseg/2)*rate)+tseg%2;
 282                 if (brp == 0 || brp > 64)
 283                         continue;
 284                 error = rate - clock/(brp*(1+tseg/2));
 285                 if (error < 0)
 286                         error = -error;
 287                 if (error <= best_error) {
 288                         best_error = error;
 289                         best_tseg = tseg/2;
 290                         best_brp = brp-1;
 291                         best_rate = clock/(brp*(1+tseg/2));
 292                 }
 293         }
 294         if (best_error && (rate/best_error < 10)) {
 295                 CANMSG("baud rate %d is not possible with %d Hz clock\n",
 296                                                                 rate, 2*clock);
 297                 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
 298                                 best_rate, best_brp, best_tseg, tseg1, tseg2);
 299                 return -EINVAL;
 300         }
 301         tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
 302         if (tseg2 < 0)
 303                 tseg2 = 0;
 304         if (tseg2 > sjaMAX_TSEG2)
 305                 tseg2 = sjaMAX_TSEG2;
 306         tseg1 = best_tseg-tseg2-2;
 307         if (tseg1>sjaMAX_TSEG1) {
 308                 tseg1 = sjaMAX_TSEG1;
 309                 tseg2 = best_tseg-tseg1-2;
 310         }
 311
 312         DEBUGMSG("Setting %d bps.\n", best_rate);
 313         DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
 314                                         best_brp, best_tseg, tseg1, tseg2,
 315                                         (100*(best_tseg-tseg2)/(best_tseg+1)));
 316
 317
 318         can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
 319         can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | (tseg2<<4)
 320                                         | tseg1, SJABTR1);
 321
 322         sja1000p_disable_configuration(chip);
 323
 324         return 0;
 325 }
 326
 327 /**
 328  * sja1000p_read: - reads and distributes one or more received messages
 329  * @chip: pointer to chip state structure
 330  * @obj: pinter to CAN message queue information
 331  *
 332  * File: src/sja1000p.c
 333  */
 334 void sja1000p_read(struct canchip_t *chip, struct msgobj_t *obj) {
 335         int i, flags, len, datastart;
 336         do {
 337                 flags = can_read_reg(chip,SJAFRM);
 338                 if(flags&sjaFRM_FF) {
 339                         obj->rx_msg.id =
 340                                 (can_read_reg(chip,SJAID0)<<21) +
 341                                 (can_read_reg(chip,SJAID1)<<13) +
 342                                 (can_read_reg(chip,SJAID2)<<5) +
 343                                 (can_read_reg(chip,SJAID3)>>3);
 344                         datastart = SJADATE;
 345                 } else {
 346                         obj->rx_msg.id =
 347                                 (can_read_reg(chip,SJAID0)<<3) +
 348                                 (can_read_reg(chip,SJAID1)>>5);
 349                         datastart = SJADATS;
 350                 }
 351                 obj->rx_msg.flags =
 352                         ((flags & sjaFRM_RTR) ? MSG_RTR : 0) |
 353                         ((flags & sjaFRM_FF) ? MSG_EXT : 0);
 354                 len = flags & sjaFRM_DLC_M;
 355                 obj->rx_msg.length = len;
 356                 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
 357                 for(i=0; i< len; i++) {
 358                         obj->rx_msg.data[i]=can_read_reg(chip,datastart+i);
 359                 }
 360
 361                 /* fill CAN message timestamp */
 362                 can_filltimestamp(&obj->rx_msg.timestamp);
 363
 364                 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
 365
 366                 can_write_reg(chip, sjaCMR_RRB, SJACMR);
 367
 368         } while (can_read_reg(chip, SJASR) & sjaSR_RBS);
 369 }
 370
 371 /**
 372  * sja1000p_pre_read_config: - prepares message object for message reception
 373  * @chip: pointer to chip state structure
 374  * @obj: pointer to message object state structure
 375  *
 376  * Return Value: negative value reports error.
 377  *      Positive value indicates immediate reception of message.
 378  * File: src/sja1000p.c
 379  */
 380 int sja1000p_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj)
 381 {
 382         int status;
 383         status=can_read_reg(chip,SJASR);
 384
 385         if(status  & sjaSR_BS) {
 386                 /* Try to recover from error condition */
 387                 DEBUGMSG("sja1000p_pre_read_config bus-off recover 0x%x\n",status);
 388                 sja1000p_enable_configuration(chip);
 389                 can_write_reg(chip, 0, SJARXERR);
 390                 can_write_reg(chip, 0, SJATXERR1);
 391                 can_read_reg(chip, SJAECC);
 392                 sja1000p_disable_configuration(chip);
 393         }
 394
 395         if (!(status&sjaSR_RBS)) {
 396                 return 0;
 397         }
 398
 399         can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER); //disable interrupts for a moment
 400         sja1000p_read(chip, obj);
 401         can_write_reg(chip, sjaENABLE_INTERRUPTS, SJAIER); //enable interrupts
 402         return 1;
 403 }
 404
 405 #define MAX_TRANSMIT_WAIT_LOOPS 10
 406 /**
 407  * sja1000p_pre_write_config: - prepares message object for message transmission
 408  * @chip: pointer to chip state structure
 409  * @obj: pointer to message object state structure
 410  * @msg: pointer to CAN message
 411  *
 412  * This function prepares selected message object for future initiation
 413  * of message transmission by sja1000p_send_msg() function.
 414  * The CAN message data and message ID are transfered from @msg slot
 415  * into chip buffer in this function.
 416  * Return Value: negative value reports error.
 417  * File: src/sja1000p.c
 418  */
 419 int sja1000p_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
 420                                                         struct canmsg_t *msg)
 421 {
 422         int i=0;
 423         unsigned int id;
 424         int status;
 425         int len;
 426
 427         /* Wait until Transmit Buffer Status is released */
 428         while ( !((status=can_read_reg(chip, SJASR)) & sjaSR_TBS) &&
 429                                                 i++<MAX_TRANSMIT_WAIT_LOOPS) {
 430                 udelay(i);
 431         }
 432
 433         if(status & sjaSR_BS) {
 434                 /* Try to recover from error condition */
 435                 DEBUGMSG("sja1000p_pre_write_config bus-off recover 0x%x\n",status);
 436                 sja1000p_enable_configuration(chip);
 437                 can_write_reg(chip, 0, SJARXERR);
 438                 can_write_reg(chip, 0, SJATXERR1);
 439                 can_read_reg(chip, SJAECC);
 440                 sja1000p_disable_configuration(chip);
 441         }
 442         if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
 443                 CANMSG("Transmit timed out, cancelling\n");
 444 // here we should check if there is no write/select waiting for this
 445 // transmit. If so, set error ret and wake up.
 446 // CHECKME: if we do not disable sjaIER_TIE (TX IRQ) here we get interrupt
 447 // immediately
 448                 can_write_reg(chip, sjaCMR_AT, SJACMR);
 449                 i=0;
 450                 while ( !(can_read_reg(chip, SJASR) & sjaSR_TBS) &&
 451                                                 i++<MAX_TRANSMIT_WAIT_LOOPS) {
 452                         udelay(i);
 453                 }
 454                 if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
 455                         CANMSG("Could not cancel, please reset\n");
 456                         return -EIO;
 457                 }
 458         }
 459         len = msg->length;
 460         if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
 461         /* len &= sjaFRM_DLC_M; ensured by above condition already */
 462         can_write_reg(chip, ((msg->flags&MSG_EXT)?sjaFRM_FF:0) |
 463                 ((msg->flags & MSG_RTR) ? sjaFRM_RTR : 0) | len, SJAFRM);
 464         if(msg->flags&MSG_EXT) {
 465                 id=msg->id<<3;
 466                 can_write_reg(chip, id & 0xff, SJAID3);
 467                 id >>= 8;
 468                 can_write_reg(chip, id & 0xff, SJAID2);
 469                 id >>= 8;
 470                 can_write_reg(chip, id & 0xff, SJAID1);
 471                 id >>= 8;
 472                 can_write_reg(chip, id, SJAID0);
 473                 for(i=0; i < len; i++) {
 474                         can_write_reg(chip, msg->data[i], SJADATE+i);
 475                 }
 476         } else {
 477                 id=msg->id<<5;
 478                 can_write_reg(chip, (id >> 8) & 0xff, SJAID0);
 479                 can_write_reg(chip, id & 0xff, SJAID1);
 480                 for(i=0; i < len; i++) {
 481                         can_write_reg(chip, msg->data[i], SJADATS+i);
 482                 }
 483         }
 484         return 0;
 485 }
 486
 487 /**
 488  * sja1000p_send_msg: - initiate message transmission
 489  * @chip: pointer to chip state structure
 490  * @obj: pointer to message object state structure
 491  * @msg: pointer to CAN message
 492  *
 493  * This function is called after sja1000p_pre_write_config() function,
 494  * which prepares data in chip buffer.
 495  * Return Value: negative value reports error.
 496  * File: src/sja1000p.c
 497  */
 498 int sja1000p_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
 499                                                         struct canmsg_t *msg)
 500 {
 501         can_write_reg(chip, sjaCMR_TR, SJACMR);
 502
 503         return 0;
 504 }
 505
 506 /**
 507  * sja1000p_check_tx_stat: - checks state of transmission engine
 508  * @chip: pointer to chip state structure
 509  *
 510  * Return Value: negative value reports error.
 511  *      Positive return value indicates transmission under way status.
 512  *      Zero value indicates finishing of all issued transmission requests.
 513  * File: src/sja1000p.c
 514  */
 515 int sja1000p_check_tx_stat(struct canchip_t *chip)
 516 {
 517         if (can_read_reg(chip,SJASR) & sjaSR_TCS)
 518                 return 0;
 519         else
 520                 return 1;
 521 }
 522
 523 /**
 524  * sja1000p_set_btregs: -  configures bitrate registers
 525  * @chip: pointer to chip state structure
 526  * @btr0: bitrate register 0
 527  * @btr1: bitrate register 1
 528  *
 529  * Return Value: negative value reports error.
 530  * File: src/sja1000p.c
 531  */
 532 int sja1000p_set_btregs(struct canchip_t *chip, unsigned short btr0,
 533                                                         unsigned short btr1)
 534 {
 535         if (sja1000p_enable_configuration(chip))
 536                 return -ENODEV;
 537
 538         can_write_reg(chip, btr0, SJABTR0);
 539         can_write_reg(chip, btr1, SJABTR1);
 540
 541         sja1000p_disable_configuration(chip);
 542
 543         return 0;
 544 }
 545
 546 /**
 547  * sja1000p_start_chip: -  starts chip message processing
 548  * @chip: pointer to chip state structure
 549  *
 550  * Return Value: negative value reports error.
 551  * File: src/sja1000p.c
 552  */
 553 int sja1000p_start_chip(struct canchip_t *chip)
 554 {
 555         enum sja1000_PeliCAN_MOD flags;
 556
 557         flags = can_read_reg(chip, SJAMOD) & (sjaMOD_LOM|sjaMOD_STM|sjaMOD_AFM|sjaMOD_SM);
 558         can_write_reg(chip, flags, SJAMOD);
 559
 560         sja1000_report_error_limit_counter=0;
 561
 562         return 0;
 563 }
 564
 565 /**
 566  * sja1000p_stop_chip: -  stops chip message processing
 567  * @chip: pointer to chip state structure
 568  *
 569  * Return Value: negative value reports error.
 570  * File: src/sja1000p.c
 571  */
 572 int sja1000p_stop_chip(struct canchip_t *chip)
 573 {
 574         enum sja1000_PeliCAN_MOD flags;
 575
 576         flags = can_read_reg(chip, SJAMOD) & (sjaMOD_LOM|sjaMOD_STM|sjaMOD_AFM|sjaMOD_SM);
 577         can_write_reg(chip, flags|sjaMOD_RM, SJAMOD);
 578
 579         return 0;
 580 }
 581
 582 /**
 583  * sja1000p_attach_to_chip: - attaches to the chip, setups registers and state
 584  * @chip: pointer to chip state structure
 585  *
 586  * Return Value: negative value reports error.
 587  * File: src/sja1000p.c
 588  */
 589 int sja1000p_attach_to_chip(struct canchip_t *chip)
 590 {
 591         return 0;
 592 }
 593
 594 /**
 595  * sja1000p_release_chip: - called before chip structure removal if %CHIP_ATTACHED is set
 596  * @chip: pointer to chip state structure
 597  *
 598  * Return Value: negative value reports error.
 599  * File: src/sja1000p.c
 600  */
 601 int sja1000p_release_chip(struct canchip_t *chip)
 602 {
 603         sja1000p_stop_chip(chip);
 604         can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER);
 605
 606         return 0;
 607 }
 608
 609 /**
 610  * sja1000p_remote_request: - configures message object and asks for RTR message
 611  * @chip: pointer to chip state structure
 612  * @obj: pointer to message object structure
 613  *
 614  * Return Value: negative value reports error.
 615  * File: src/sja1000p.c
 616  */
 617 int sja1000p_remote_request(struct canchip_t *chip, struct msgobj_t *obj)
 618 {
 619         CANMSG("sja1000p_remote_request not implemented\n");
 620         return -ENOSYS;
 621 }
 622
 623 /**
 624  * sja1000p_standard_mask: - setup of mask for message filtering
 625  * @chip: pointer to chip state structure
 626  * @code: can message acceptance code
 627  * @mask: can message acceptance mask
 628  *
 629  * Return Value: negative value reports error.
 630  * File: src/sja1000p.c
 631  */
 632 int sja1000p_standard_mask(struct canchip_t *chip, unsigned short code,
 633                 unsigned short mask)
 634 {
 635         CANMSG("sja1000p_standard_mask not implemented\n");
 636         return -ENOSYS;
 637 }
 638
 639 /**
 640  * sja1000p_clear_objects: - clears state of all message object residing in chip
 641  * @chip: pointer to chip state structure
 642  *
 643  * Return Value: negative value reports error.
 644  * File: src/sja1000p.c
 645  */
 646 int sja1000p_clear_objects(struct canchip_t *chip)
 647 {
 648         CANMSG("sja1000p_clear_objects not implemented\n");
 649         return -ENOSYS;
 650 }
 651
 652 /**
 653  * sja1000p_config_irqs: - tunes chip hardware interrupt delivery
 654  * @chip: pointer to chip state structure
 655  * @irqs: requested chip IRQ configuration
 656  *
 657  * Return Value: negative value reports error.
 658  * File: src/sja1000p.c
 659  */
 660 int sja1000p_config_irqs(struct canchip_t *chip, short irqs)
 661 {
 662         CANMSG("sja1000p_config_irqs not implemented\n");
 663         return -ENOSYS;
 664 }
 665
 666 /**
 667  * sja1000p_irq_write_handler: - part of ISR code responsible for transmit events
 668  * @chip: pointer to chip state structure
 669  * @obj: pointer to attached queue description
 670  *
 671  * The main purpose of this function is to read message from attached queues
 672  * and transfer message contents into CAN controller chip.
 673  * This subroutine is called by
 674  * sja1000p_irq_write_handler() for transmit events.
 675  * File: src/sja1000p.c
 676  */
 677 void sja1000p_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj)
 678 {
 679         int cmd;
 680
 681         if(obj->tx_slot){
 682                 /* Do local transmitted message distribution if enabled */
 683                 if (processlocal){
 684                         /* fill CAN message timestamp */
 685                         can_filltimestamp(&obj->tx_slot->msg.timestamp);
 686
 687                         obj->tx_slot->msg.flags |= MSG_LOCAL;
 688                         canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
 689                 }
 690                 /* Free transmitted slot */
 691                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 692                 obj->tx_slot=NULL;
 693         }
 694
 695         can_msgobj_clear_fl(obj,TX_PENDING);
 696         cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
 697         if(cmd<0)
 698                 return;
 699         can_msgobj_set_fl(obj,TX_PENDING);
 700
 701         if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
 702                 obj->ret = -1;
 703                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
 704                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 705                 obj->tx_slot=NULL;
 706                 return;
 707         }
 708         if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
 709                 obj->ret = -1;
 710                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
 711                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 712                 obj->tx_slot=NULL;
 713                 return;
 714         }
 715
 716 }
 717
 718 #define MAX_RETR 10
 719
 720 /**
 721  * sja1000p_irq_handler: - interrupt service routine
 722  * @irq: interrupt vector number, this value is system specific
 723  * @chip: pointer to chip state structure
 724  *
 725  * Interrupt handler is activated when state of CAN controller chip changes,
 726  * there is message to be read or there is more space for new messages or
 727  * error occurs. The receive events results in reading of the message from
 728  * CAN controller chip and distribution of message through attached
 729  * message queues.
 730  * File: src/sja1000p.c
 731  */
 732 int sja1000p_irq_handler(int irq, struct canchip_t *chip)
 733 {
 734         int irq_register, status, error_code;
 735         struct msgobj_t *obj=chip->msgobj[0];
 736         int loop_cnt=CHIP_MAX_IRQLOOP;
 737
 738         irq_register=can_read_reg(chip,SJAIR);
 739 //      DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
 740 //      DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
 741 //                                      can_read_reg(chip,SJASR));
 742
 743         if ((irq_register & (sjaIR_BEI|sjaIR_EPI|sjaIR_DOI|sjaIR_EI|sjaIR_TI|sjaIR_RI)) == 0)
 744                 return CANCHIP_IRQ_NONE;
 745
 746         if(!(chip->flags&CHIP_CONFIGURED)) {
 747                 CANMSG("sja1000p_irq_handler: called for non-configured device, irq_register 0x%02x\n", irq_register);
 748                 return CANCHIP_IRQ_NONE;
 749         }
 750
 751         status=can_read_reg(chip,SJASR);
 752
 753         do {
 754
 755                 if(!loop_cnt--) {
 756                         CANMSG("sja1000p_irq_handler IRQ %d stuck\n",irq);
 757                         return CANCHIP_IRQ_STUCK;
 758                 }
 759
 760                 /* (irq_register & sjaIR_RI) */
 761                 /*      old variant using SJAIR, collides with intended use with irq_accept */
 762                 if (status & sjaSR_RBS) {
 763                         DEBUGMSG("sja1000_irq_handler: RI or RBS\n");
 764                         sja1000p_read(chip,obj);
 765                         obj->ret = 0;
 766                 }
 767
 768                 /* (irq_register & sjaIR_TI) */
 769                 /*      old variant using SJAIR, collides with intended use with irq_accept */
 770                 if ((status & sjaSR_TBS) && can_msgobj_test_fl(obj,TX_PENDING)) {
 771                         DEBUGMSG("sja1000_irq_handler: TI or TX_PENDING and TBS\n");
 772                         obj->ret = 0;
 773                         can_msgobj_set_fl(obj,TX_REQUEST);
 774                         while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
 775                                 can_msgobj_clear_fl(obj,TX_REQUEST);
 776
 777                                 if (can_read_reg(chip, SJASR) & sjaSR_TBS)
 778                                         sja1000p_irq_write_handler(chip, obj);
 779
 780                                 can_msgobj_clear_fl(obj,TX_LOCK);
 781                                 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
 782                                 DEBUGMSG("TX looping in sja1000_irq_handler\n");
 783                         }
 784                 }
 785                 if ((irq_register & (sjaIR_EI|sjaIR_BEI|sjaIR_EPI|sjaIR_DOI)) != 0) {
 786                         // Some error happened
 787                         error_code=can_read_reg(chip,SJAECC);
 788                         sja1000_report_error(chip, status, irq_register, error_code);
 789 // FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
 790 // Reset flag set to 0 if chip is already off the bus. Full state report
 791                         obj->ret=-1;
 792
 793                         if(error_code == 0xd9) {
 794                                 obj->ret= -ENXIO;
 795                                 /* no such device or address - no ACK received */
 796                         }
 797                         if(obj->tx_retry_cnt++>MAX_RETR) {
 798                                 can_write_reg(chip, sjaCMR_AT, SJACMR); // cancel any transmition
 799                                 obj->tx_retry_cnt = 0;
 800                         }
 801                         if(status&sjaSR_BS) {
 802                                 CANMSG("bus-off, resetting sja1000p\n");
 803                                 can_write_reg(chip, 0, SJAMOD);
 804                         }
 805
 806                         if(obj->tx_slot){
 807                                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_BUS);
 808                                 /*canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 809                                 obj->tx_slot=NULL;*/
 810                         }
 811
 812                 } else {
 813                         if(sja1000_report_error_limit_counter)
 814                                 sja1000_report_error_limit_counter--;
 815                         obj->tx_retry_cnt=0;
 816                 }
 817
 818                 irq_register=can_read_reg(chip,SJAIR);
 819
 820                 status=can_read_reg(chip,SJASR);
 821
 822                 if(((status & sjaSR_TBS) && can_msgobj_test_fl(obj,TX_PENDING)) ||
 823                    (irq_register & sjaIR_TI))
 824                          can_msgobj_set_fl(obj,TX_REQUEST);
 825
 826         } while((irq_register & (sjaIR_BEI|sjaIR_EPI|sjaIR_DOI|sjaIR_EI|sjaIR_RI)) ||
 827                 (can_msgobj_test_fl(obj,TX_PENDING) && !can_msgobj_test_fl(obj,TX_LOCK)) ||
 828                 (status & sjaSR_RBS));
 829
 830         return CANCHIP_IRQ_HANDLED;
 831 }
 832
 833 /**
 834  * sja1000p_wakeup_tx: - wakeups TX processing
 835  * @chip: pointer to chip state structure
 836  * @obj: pointer to message object structure
 837  *
 838  * Function is responsible for initiating message transmition.
 839  * It is responsible for clearing of object TX_REQUEST flag
 840  *
 841  * Return Value: negative value reports error.
 842  * File: src/sja1000p.c
 843  */
 844 int sja1000p_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
 845 {
 846
 847         can_preempt_disable();
 848
 849         can_msgobj_set_fl(obj,TX_PENDING);
 850         can_msgobj_set_fl(obj,TX_REQUEST);
 851         while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
 852                 can_msgobj_clear_fl(obj,TX_REQUEST);
 853
 854                 if (can_read_reg(chip, SJASR) & sjaSR_TBS){
 855                         obj->tx_retry_cnt=0;
 856                         sja1000p_irq_write_handler(chip, obj);
 857                 }
 858
 859                 can_msgobj_clear_fl(obj,TX_LOCK);
 860                 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
 861                 DEBUGMSG("TX looping in sja1000p_wakeup_tx\n");
 862         }
 863
 864         can_preempt_enable();
 865         return 0;
 866 }
 867
 868 int sja1000p_register(struct chipspecops_t *chipspecops)
 869 {
 870         CANMSG("initializing sja1000p chip operations\n");
 871         chipspecops->chip_config=sja1000p_chip_config;
 872         chipspecops->baud_rate=sja1000p_baud_rate;
 873         chipspecops->standard_mask=sja1000p_standard_mask;
 874         chipspecops->extended_mask=sja1000p_extended_mask;
 875         chipspecops->message15_mask=sja1000p_extended_mask;
 876         chipspecops->clear_objects=sja1000p_clear_objects;
 877         chipspecops->config_irqs=sja1000p_config_irqs;
 878         chipspecops->pre_read_config=sja1000p_pre_read_config;
 879         chipspecops->pre_write_config=sja1000p_pre_write_config;
 880         chipspecops->send_msg=sja1000p_send_msg;
 881         chipspecops->check_tx_stat=sja1000p_check_tx_stat;
 882         chipspecops->wakeup_tx=sja1000p_wakeup_tx;
 883         chipspecops->remote_request=sja1000p_remote_request;
 884         chipspecops->enable_configuration=sja1000p_enable_configuration;
 885         chipspecops->disable_configuration=sja1000p_disable_configuration;
 886         chipspecops->attach_to_chip=sja1000p_attach_to_chip;
 887         chipspecops->release_chip=sja1000p_release_chip;
 888         chipspecops->set_btregs=sja1000p_set_btregs;
 889         chipspecops->start_chip=sja1000p_start_chip;
 890         chipspecops->stop_chip=sja1000p_stop_chip;
 891         chipspecops->irq_handler=sja1000p_irq_handler;
 892         chipspecops->irq_accept=NULL;
 893         return 0;
 894 }
 895
 896 /**
 897  * sja1000p_fill_chipspecops - fills chip specific operations
 898  * @chip: pointer to chip representation structure
 899  *
 900  * The function fills chip specific operations for sja1000 (PeliCAN) chip.
 901  *
 902  * Return Value: returns negative number in the case of fail
 903  */
 904 int sja1000p_fill_chipspecops(struct canchip_t *chip)
 905 {
 906         chip->chip_type="sja1000p";
 907         chip->max_objects=1;
 908         sja1000p_register(chip->chipspecops);
 909         return 0;
 910 }