2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * This software is released under the GPL-License.
5 * Version 0.6 18 Sept 2000
8 #include <linux/autoconf.h>
9 #if defined (CONFIG_MODVERSIONS) && !defined (MODVERSIONS)
13 #if defined (MODVERSIONS)
14 #include <linux/modversions.h>
17 #include <linux/delay.h>
20 #include "../include/main.h"
21 #include "../include/sja1000.h"
23 int sja1000_enable_configuration(struct chip_t *chip)
28 disable_irq(chip->chip_irq);
30 flags=can_read_reg(chip,SJACR);
32 while ((!(flags & CR_RR)) && (i<=10)) {
33 can_write_reg(chip,flags|CR_RR,SJACR);
36 flags=can_read_reg(chip,SJACR);
39 CANMSG("Reset error\n");
40 enable_irq(chip->chip_irq);
47 int sja1000_disable_configuration(struct chip_t *chip)
52 flags=can_read_reg(chip,SJACR);
54 while ( (flags & CR_RR) && (i<=10) ) {
55 can_write_reg(chip,flags & (CR_RIE|CR_TIE|CR_EIE|CR_OIE),SJACR);
58 flags=can_read_reg(chip,SJACR);
61 CANMSG("Error leaving reset status\n");
65 enable_irq(chip->chip_irq);
70 int sja1000_chip_config(struct chip_t *chip)
72 if (sja1000_enable_configuration(chip))
75 /* Set mode, clock out, comparator */
76 can_write_reg(chip,chip->sja_cdr_reg,SJACDR);
77 /* Set driver output configuration */
78 can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
80 if (sja1000_standard_mask(chip,0x0000, 0xffff))
85 if (sja1000_baud_rate(chip,1000*baudrate,chip->clock,0,75,0))
88 /* Enable hardware interrupts */
89 can_write_reg(chip,(CR_RIE|CR_TIE|CR_EIE|CR_OIE),SJACR);
91 sja1000_disable_configuration(chip);
96 int sja1000_standard_mask(struct chip_t *chip, unsigned short code, unsigned short mask)
98 unsigned char write_code, write_mask;
100 if (sja1000_enable_configuration(chip))
103 /* The acceptance code bits (SJAACR bits 0-7) and the eight most
104 * significant bits of the message identifier (id.10 to id.3) must be
105 * equal to those bit positions which are marked relevant by the
106 * acceptance mask bits (SJAAMR bits 0-7).
107 * (id.10 to id.3) = (SJAACR.7 to SJAACR.0) v (SJAAMR.7 to SJAAMR.0)
108 * (Taken from Philips sja1000 Data Sheet)
110 write_code = (unsigned char) code >> 3;
111 write_mask = (unsigned char) mask >> 3;
113 can_write_reg(chip,write_code,SJAACR);
114 can_write_reg(chip,write_mask,SJAAMR);
116 DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
117 DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
119 sja1000_disable_configuration(chip);
124 /* Set communication parameters.
125 * param rate baud rate in Hz
126 * param clock frequency of sja1000 clock in Hz (ISA osc is 14318000)
127 * param sjw synchronization jump width (0-3) prescaled clock cycles
128 * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
129 * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
131 int sja1000_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
132 int sampl_pt, int flags)
134 int best_error = 1000000000, error;
135 int best_tseg=0, best_brp=0, best_rate=0, brp=0;
136 int tseg=0, tseg1=0, tseg2=0;
138 if (sja1000_enable_configuration(chip))
143 /* tseg even = round down, odd = round up */
144 for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
145 brp = clock/((1+tseg/2)*rate)+tseg%2;
146 if (brp == 0 || brp > 64)
148 error = rate - clock/(brp*(1+tseg/2));
151 if (error <= best_error) {
155 best_rate = clock/(brp*(1+tseg/2));
158 if (best_error && (rate/best_error < 10)) {
159 CANMSG("baud rate %d is not possible with %d Hz clock\n",
161 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
162 best_rate, best_brp, best_tseg, tseg1, tseg2);
165 tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
168 if (tseg2 > MAX_TSEG2)
170 tseg1 = best_tseg-tseg2-2;
171 if (tseg1 > MAX_TSEG1) {
173 tseg2 = best_tseg-tseg1-2;
176 DEBUGMSG("Setting %d bps.\n", best_rate);
177 DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
178 best_brp, best_tseg, tseg1, tseg2,
179 (100*(best_tseg-tseg2)/(best_tseg+1)));
182 can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
183 can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | tseg2<<4 | tseg1,
185 // can_write_reg(chip, OCR_MODE_NORMAL | OCR_TX0_LH | OCR_TX1_ZZ, SJAOCR);
186 /* BASIC mode, bypass input comparator */
187 // can_write_reg(chip, CDR_CBP| /* CDR_CLK_OFF | */ 7, SJACDR);
189 sja1000_disable_configuration(chip);
194 int sja1000_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
197 struct canfifo_t *fifo = chip->msgobj[0]->fifo;
199 i=can_read_reg(chip,SJASR);
203 for (i=0; i<0x20; i++)
204 CANMSG("0x%x is 0x%x\n",i,can_read_reg(chip,i));
207 sja1000_start_chip(chip);
209 can_write_reg(chip, 0, SJACR); // disable interrupts for a moment
210 // TODO: this would be best sja1000_irq_read_handler(chip);
211 // now just duplicate the code.
213 id=(can_read_reg(chip, SJARXID1)<<8) + can_read_reg(chip,
215 fifo->buf_rx_entry[fifo->head].length = (id>>8) & 0x0f;
216 fifo->buf_rx_entry[fifo->head].id = id>>5;
217 fifo->buf_rx_entry[fifo->head].flags = id&ID0_RTR ?
219 fifo->buf_rx_entry[fifo->head].timestamp = 0;
220 fifo->buf_rx_entry[fifo->head].cob = 0;
221 for (i=0; i<fifo->buf_rx_entry[fifo->head].length; i++) {
222 fifo->buf_rx_entry[fifo->head].data[i] =
223 can_read_reg(chip,SJARXDAT0 + i);
226 if (fifo->head == MAX_BUF_LENGTH -1)
228 can_write_reg(chip, CMR_RRB, SJACMR);
229 } while (can_read_reg(chip, SJASR) & SR_RBS);
232 can_write_reg(chip, CR_OIE | CR_EIE | CR_TIE | CR_RIE, SJACR);
238 #define MAX_TRANSMIT_WAIT_LOOPS 200
239 int sja1000_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
240 struct canmsg_t *msg)
244 sja1000_start_chip(chip); //sja1000 goes automatically into reset mode on errors
246 /* Wait until Transmit Buffer Status is released */
247 while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
248 i++<MAX_TRANSMIT_WAIT_LOOPS) {
252 if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
253 CANMSG("Transmit timed out, cancelling\n");
254 can_write_reg(chip, CMR_AT, SJACMR);
256 while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
257 i++<MAX_TRANSMIT_WAIT_LOOPS) {
260 if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
261 CANMSG("Could not cancel, please reset\n");
266 id = (msg->id<<5) | ((msg->flags&MSG_RTR)?ID0_RTR:0) | msg->length;
268 can_write_reg(chip, id>>8, SJATXID1);
269 can_write_reg(chip, id & 0xff , SJATXID0);
271 for (i=0; i<msg->length; i++)
272 can_write_reg(chip, msg->data[i], SJATXDAT0+i);
277 int sja1000_send_msg(struct chip_t *chip, struct msgobj_t *obj,
278 struct canmsg_t *msg)
280 can_write_reg(chip, CMR_TR, SJACMR);
285 int sja1000_check_tx_stat(struct chip_t *chip)
287 if (can_read_reg(chip,SJASR) & SR_TCS)
293 int sja1000_set_btregs(struct chip_t *chip, unsigned short btr0,
296 if (sja1000_enable_configuration(chip))
299 can_write_reg(chip, btr0, SJABTR0);
300 can_write_reg(chip, btr1, SJABTR1);
302 sja1000_disable_configuration(chip);
307 int sja1000_start_chip(struct chip_t *chip)
309 unsigned short flags = 0;
311 flags = can_read_reg(chip, SJACR) & (CR_RIE|CR_TIE|CR_EIE|CR_OIE);
312 can_write_reg(chip, flags, SJACR);
317 int sja1000_stop_chip(struct chip_t *chip)
319 unsigned short flags = 0;
321 flags = can_read_reg(chip, SJACR) & (CR_RIE|CR_TIE|CR_EIE|CR_OIE);
322 can_write_reg(chip, flags|CR_RR, SJACR);
327 int sja1000_remote_request(struct chip_t *chip, struct msgobj_t *obj)
329 CANMSG("sja1000_remote_request not implemented\n");
333 int sja1000_extended_mask(struct chip_t *chip, unsigned long code,
336 CANMSG("sja1000_extended_mask not implemented\n");
340 int sja1000_clear_objects(struct chip_t *chip)
342 CANMSG("sja1000_clear_objects not implemented\n");
346 int sja1000_config_irqs(struct chip_t *chip, short irqs)
348 CANMSG("sja1000_config_irqs not implemented\n");
352 int sja1000_register(struct chipspecops_t *chipspecops)
354 chipspecops->chip_config = sja1000_chip_config;
355 chipspecops->baud_rate = sja1000_baud_rate;
356 chipspecops->standard_mask = sja1000_standard_mask;
357 chipspecops->extended_mask = sja1000_extended_mask;
358 chipspecops->message15_mask = sja1000_extended_mask;
359 chipspecops->clear_objects = sja1000_clear_objects;
360 chipspecops->config_irqs = sja1000_config_irqs;
361 chipspecops->pre_read_config = sja1000_pre_read_config;
362 chipspecops->pre_write_config = sja1000_pre_write_config;
363 chipspecops->send_msg = sja1000_send_msg;
364 chipspecops->check_tx_stat = sja1000_check_tx_stat;
365 chipspecops->remote_request = sja1000_remote_request;
366 chipspecops->enable_configuration = sja1000_enable_configuration;
367 chipspecops->disable_configuration = sja1000_disable_configuration;
368 chipspecops->set_btregs = sja1000_set_btregs;
369 chipspecops->start_chip = sja1000_start_chip;
370 chipspecops->stop_chip = sja1000_stop_chip;
371 chipspecops->irq_handler = sja1000_irq_handler;