2 * Header file for the Linux CAN-bus driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * This software is released under the GPL-License.
5 * Version 0.7 6 Aug 2001
8 int sja1000_enable_configuration(struct chip_t *chip);
9 int sja1000_disable_configuration(struct chip_t *chip);
10 int sja1000_chip_config(struct chip_t *chip);
11 int sja1000_standard_mask(struct chip_t *chip, unsigned short code, unsigned short mask);
12 int sja1000_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
13 int sampl_pt, int flags);
14 int sja1000_pre_read_config(struct chip_t *chip, struct msgobj_t *obj);
15 int sja1000_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
16 struct canmsg_t *msg);
17 int sja1000_send_msg(struct chip_t *chip, struct msgobj_t *obj,
18 struct canmsg_t *msg);
19 int sja1000_check_tx_stat(struct chip_t *chip);
20 int sja1000_set_btregs(struct chip_t *chip, unsigned short btr0,
22 int sja1000_start_chip(struct chip_t *chip);
23 int sja1000_stop_chip(struct chip_t *chip);
24 void sja1000_irq_handler(int irq, void *dev_id, struct pt_regs *regs);
26 /* BasicCAN mode address map */
27 #define SJACR 0x00 /* Control register */
28 #define SJACMR 0x01 /* Command register */
29 #define SJASR 0x02 /* Status register */
30 #define SJAIR 0x03 /* Interrupt register */
31 #define SJAACR 0x04 /* Acceptance Code register */
32 #define SJAAMR 0x05 /* Acceptance Mask Register */
33 #define SJABTR0 0x06 /* Bus Timing register 0 */
34 #define SJABTR1 0x07 /* Bus Timing register 1 */
35 #define SJAOCR 0x08 /* Output Control register */
36 #define SJACDR 0x1f /* Clock Divider register */
38 #define SJATXID1 0x0a /* Identifier byte 1 */
39 #define SJATXID0 0x0b /* Identifier byte 0 */
40 #define SJATXDAT0 0x0c /* First data byte */
41 #define SJATXDAT1 0x0d
42 #define SJATXDAT2 0x0e
43 #define SJATDDAT3 0x0f
44 #define SJATXDAT4 0x10
45 #define SJATXDAT5 0x11
46 #define SJATXDAT6 0x12
47 #define SJATXDAT7 0x13
49 #define SJARXID1 0x14 /* Identifier byte 1 */
50 #define SJARXID0 0x15 /* Identifier byte 0 */
51 #define SJARXDAT0 0x16 /* First data byte */
52 #define SJARXDAT1 0x17
53 #define SJARXDAT2 0x18
54 #define SJARXDAT3 0x19
55 #define SJARXDAT4 0x1a
56 #define SJARXDAT5 0x1b
57 #define SJARXDAT6 0x1c
58 #define SJARXDAT7 0x1d
60 /* Command register */
61 enum sja1000_BASIC_CMR {
62 CMR_TR = 1, // Transmission request
63 CMR_AT = 1<<1, // Abort Transmission
64 CMR_RRB = 1<<2, // Release Receive Buffer
65 CMR_CDO = 1<<3, // Clear Data Overrun
66 CMR_GTS = 1<<4 // Go To Sleep
70 enum sja1000_BASIC_SR {
71 SR_RBS = 1, // Receive Buffer Status
72 SR_DOS = 1<<1, // Data Overrun Status
73 SR_TBS = 1<<2, // Transmit Buffer Status
74 SR_TCS = 1<<3, // Transmission Complete Status
75 SR_RS = 1<<4, // Receive Status
76 SR_TS = 1<<5, // Transmit Status
77 SR_ES = 1<<6, // Error Status
78 SR_BS = 1<<7 // Bus Status
81 /* Control Register */
82 enum sja1000_BASIC_CR {
83 CR_RR = 1, // Reset Request
84 CR_RIE = 1<<1, // Receive Interrupt Enable
85 CR_TIE = 1<<2, // Transmit Interrupt Enable
86 CR_EIE = 1<<3, // Error Interrupt Enable
87 CR_OIE = 1<<4 // Overrun Interrupt Enable
90 /* Interrupt (status) Register */
91 enum sja1000_BASIC_IR {
92 IR_RI = 1, // Receive Interrupt
93 IR_TI = 1<<1, // Transmit Interrupt
94 IR_EI = 1<<2, // Error Interrupt
95 IR_DOI = 1<<3, // Data Overrun Interrupt
96 IR_WUI = 1<<4 // Wake-Up Interrupt
99 /* Clock Divider Register */
101 /* f_out = f_osc/(2*(CDR[2:0]+1)) or f_osc if CDR[2:0]==7 */
103 CDR_CLK_OFF = 1<<3, // Clock Off
104 CDR_RXINPEN = 1<<5, // TX1 output is RX irq output
105 CDR_CBP = 1<<6, // Input Comparator By-Pass
106 CDR_PELICAN = 1<<7 // PeliCAN Mode
109 /* Output Control Register */
111 OCR_MODE_BIPHASE = 0,
115 // TX0 push-pull not inverted
117 // TX0 push-pull inverted
119 // TX1 floating (off)
121 // TX1 pull-down not inverted
125 /** Frame format information 0x11 */
126 enum sja1000_BASIC_ID0 {
127 ID0_RTR = 1<<4, // Remote request
128 ID0_DLC_M = (1<<4)-1 // Length Mask