2 * Header file for the Linux CAN-bus driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.2 9 Jul 2003
11 #include "./constants.h"
12 #include "./can_sysdep.h"
13 #include "./can_queue.h"
16 #define DEBUGMSG(fmt,args...) printk(KERN_ERR "can.o (debug): " fmt,\
19 #define DEBUGMSG(fmt,args...)
22 #define CANMSG(fmt,args...) printk(KERN_ERR "can.o: " fmt,##args)
26 * struct canhardware_t - structure representing pointers to all CAN boards
27 * @nr_boards: number of present boards
28 * @rtr_queue: RTR - remote transmission request queue (expect some changes there)
29 * @rtr_lock: locking for RTR queue
30 * @candevice: array of pointers to CAN devices/boards
32 struct canhardware_t {
34 struct rtr_id *rtr_queue;
35 can_spinlock_t rtr_lock;
36 struct candevice_t *candevice[MAX_HW_CARDS];
40 * struct candevice_t - CAN device/board structure
41 * @hwname: text string with board type
42 * @candev_idx: board index in canhardware_t.candevice[]
43 * @io_addr: IO/physical MEM address
44 * @res_addr: optional reset register port
45 * @dev_base_addr: CPU translated IO/virtual MEM address
46 * @flags: board flags: %PROGRAMMABLE_IRQ .. interrupt number
47 * can be programmed into board
48 * @nr_all_chips: number of chips present on the board
49 * @nr_82527_chips: number of Intel 8257 chips
50 * @nr_sja1000_chips: number of Philips SJA100 chips
51 * @chip: array of pointers to the chip structures
52 * @hwspecops: pointer to board specific operations
53 * @hosthardware_p: pointer to the root hardware structure
55 * The structure represent configuration and state of associated board.
56 * The driver infrastructure prepares this structure and calls
57 * board type specific board_register() function. The board support provided
58 * register function fills right function pointers in @hwspecops structure.
59 * Then driver setup calls functions init_hw_data(), init_chip_data(),
60 * init_chip_data(), init_obj_data() and program_irq(). Function init_hw_data()
61 * and init_chip_data() have to specify number and types of connected chips
62 * or objects respectively.
63 * The use of @nr_all_chips is preferred over use of fields @nr_82527_chips
64 * and @nr_sja1000_chips in the board non-specific functions.
65 * The @io_addr and @dev_base_addr is filled from module parameters
66 * to the same value. The request_io function can fix-up @dev_base_addr
67 * field if virtual address is different than bus address.
70 char *hwname; /* text board type */
71 int candev_idx; /* board index in canhardware_t.candevice[] */
72 unsigned long io_addr; /* IO/physical MEM address */
73 unsigned long res_addr; /* optional seset register port */
74 unsigned long dev_base_addr; /* CPU translated IO/virtual MEM address */
79 struct chip_t *chip[MAX_HW_CHIPS];
81 struct hwspecops_t *hwspecops;
83 struct canhardware_t *hosthardware_p;
87 * struct chip_t - CAN chip state and type information
88 * @chip_type: text string describing chip type
89 * @chip_idx: index of the chip in candevice_t.chip[] array
90 * @chip_irq: chip interrupt number if any
91 * @chip_base_addr: chip base address in the CPU IO or virtual memory space
92 * @flags: chip flags: %CHIP_CONFIGURED .. chip is configured,
93 * %CHIP_SEGMENTED .. access to the chip is segmented (mainly for i82527 chips)
94 * @clock: chip base clock frequency in Hz
95 * @baudrate: selected chip baudrate in Hz
96 * @write_register: write chip register function copy -
97 * @read_register: read chip register function copy
98 * @sja_cdr_reg: SJA specific register -
99 * holds hardware specific options for the Clock Divider
100 * register. Options defined in the sja1000.h file:
101 * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
102 * @sja_ocr_reg: SJA specific register -
103 * hold hardware specific options for the Output Control
104 * register. Options defined in the sja1000.h file:
105 * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
106 * %OCR_TX0_LH, %OCR_TX1_ZZ.
107 * @int_cpu_reg: Intel specific register -
108 * holds hardware specific options for the CPU Interface
109 * register. Options defined in the i82527.h file:
110 * %iCPU_CEN, %iCPU_MUX, %iCPU_SLP, %iCPU_PWD, %iCPU_DMC, %iCPU_DSC, %iCPU_RST.
111 * @int_clk_reg: Intel specific register -
112 * holds hardware specific options for the Clock Out
113 * register. Options defined in the i82527.h file:
114 * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
115 * @int_bus_reg: Intel specific register -
116 * holds hardware specific options for the Bus Configuration
117 * register. Options defined in the i82527.h file:
118 * %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY.
119 * @msgobj: array of pointers to individual communication objects
120 * @chipspecops: pointer to the set of chip specific object filled by init_chip_data() function
121 * @hostdevice: pointer to chip hosting board
122 * @max_objects: maximal number of communication objects connected to this chip
124 * The fields @write_register and @read_register are copied from
125 * corresponding fields from @hwspecops structure
126 * (chip->hostdevice->hwspecops->write_register and
127 * chip->hostdevice->hwspecops->read_register)
128 * to speedup can_write_reg() and can_read_reg() functions.
132 int chip_idx; /* chip index in candevice_t.chip[] */
134 unsigned long chip_base_addr;
136 long clock; /* Chip clock in Hz */
139 void (*write_register)(unsigned char data,unsigned long address);
140 unsigned (*read_register)(unsigned long address);
142 unsigned short sja_cdr_reg; /* sja1000 only! */
143 unsigned short sja_ocr_reg; /* sja1000 only! */
144 unsigned short int_cpu_reg; /* intel 82527 only! */
145 unsigned short int_clk_reg; /* intel 82527 only! */
146 unsigned short int_bus_reg; /* intel 82527 only! */
148 struct msgobj_t *msgobj[MAX_MSGOBJS];
150 struct chipspecops_t *chipspecops;
152 struct candevice_t *hostdevice;
154 int max_objects; /* 1 for sja1000, 15 for i82527 */
158 * struct msgobj_t - structure holding communication object state
160 * @minor: associated device minor number
161 * @object: object number in chip_t structure +1
162 * @flags: message object flags
163 * @ret: field holding status of the last Tx operation
164 * @qends: pointer to message object corresponding ends structure
165 * @tx_qedge: edge corresponding to transmitted message
166 * @tx_slot: slot holding transmitted message, slot is taken from
167 * canque_test_outslot() call and is freed by canque_free_outslot()
168 * or rescheduled canque_again_outslot()
169 * @tx_retry_cnt: transmission attempt counter
170 * @tx_timeout: can be used by chip driver to check for the transmission timeout
171 * @rx_msg: temporary storage to hold received messages before
172 * calling to canque_filter_msg2edges()
173 * @hostchip: pointer to the &chip_t structure this object belongs to
174 * @obj_used: counter of users (associated file structures for Linux
175 * userspace clients) of this object
176 * @obj_users: list of user structures of type &canuser_t.
179 unsigned long obj_base_addr;
180 unsigned int minor; /* associated device minor number */
181 unsigned int object; /* object number in chip_t +1 for debug printk */
185 struct canque_ends_t *qends;
187 struct canque_edge_t *tx_qedge;
188 struct canque_slot_t *tx_slot;
190 struct timer_list tx_timeout;
192 struct canmsg_t rx_msg;
194 struct chip_t *hostchip;
197 struct list_head obj_users;
200 #define CAN_USER_MAGIC 0x05402033
203 * struct canuser_t - structure holding CAN user/client state
204 * @peers: for connection into list of object users
205 * @qends: pointer to the ends structure corresponding for this user
206 * @file: pointer to open device file state structure
207 * @msgobj: communication object the user is connected to
208 * @rx_edge0: default receive queue for filter IOCTL
209 * @magic: magic number to check consistency when pointer is retrieved
210 * from file private field
213 struct list_head peers;
214 struct canque_ends_t *qends;
215 struct file *file; /* back ptr to file */
216 struct msgobj_t *msgobj;
217 struct canque_edge_t *rx_edge0; /* simplifies IOCTL */
222 * struct hwspecops_t - hardware/board specific operations
223 * @request_io: reserve io or memory range for can board
224 * @release_io: free reserved io memory range
225 * @reset: hardware reset routine
226 * @init_hw_data: called to initialize &candevice_t structure, mainly
227 * @res_add, @nr_all_chips, @nr_82527_chips, @nr_sja1000_chips
229 * @init_chip_data: called initialize each &chip_t structure, mainly
230 * @chip_type, @chip_base_addr, @clock and chip specific registers.
231 * It is responsible to setup &chip_t->@chipspecops functions
232 * for non-standard chip types (type other than "i82527", "sja1000" or "sja1000p")
233 * @init_obj_data: called initialize each &msgobj_t structure,
234 * mainly @obj_base_addr field.
235 * @program_irq: program interrupt generation hardware of the board
236 * if flag %PROGRAMMABLE_IRQ is present for specified device/board
237 * @write_register: low level write register routine
238 * @read_register: low level read register routine
241 int (*request_io)(struct candevice_t *candev);
242 int (*release_io)(struct candevice_t *candev);
243 int (*reset)(struct candevice_t *candev);
244 int (*init_hw_data)(struct candevice_t *candev);
245 int (*init_chip_data)(struct candevice_t *candev, int chipnr);
246 int (*init_obj_data)(struct chip_t *chip, int objnr);
247 int (*program_irq)(struct candevice_t *candev);
248 void (*write_register)(unsigned char data,unsigned long address);
249 unsigned (*read_register)(unsigned long address);
253 * struct chipspecops_t - can controller chip specific operations
254 * @chip_config: CAN chip configuration
255 * @baud_rate: set communication parameters
256 * @standard_mask: setup of mask for message filtering
257 * @extended_mask: setup of extended mask for message filtering
258 * @message15_mask: set mask of i82527 message object 15
259 * @clear_objects: clears state of all message object residing in chip
260 * @config_irqs: tunes chip hardware interrupt delivery
261 * @pre_read_config: prepares message object for message reception
262 * @pre_write_config: prepares message object for message transmission
263 * @send_msg: initiate message transmission
264 * @remote_request: configures message object and asks for RTR message
265 * @check_tx_stat: checks state of transmission engine
266 * @wakeup_tx: wakeup TX processing
267 * @enable_configuration: enable chip configuration mode
268 * @disable_configuration: disable chip configuration mode
269 * @set_btregs: configures bitrate registers
270 * @start_chip: starts chip message processing
271 * @stop_chip: stops chip message processing
272 * @irq_handler: interrupt service routine
274 struct chipspecops_t {
275 int (*chip_config)(struct chip_t *chip);
276 int (*baud_rate)(struct chip_t *chip, int rate, int clock, int sjw,
277 int sampl_pt, int flags);
278 int (*standard_mask)(struct chip_t *chip, unsigned short code,
279 unsigned short mask);
280 int (*extended_mask)(struct chip_t *chip, unsigned long code,
282 int (*message15_mask)(struct chip_t *chip, unsigned long code,
284 int (*clear_objects)(struct chip_t *chip);
285 int (*config_irqs)(struct chip_t *chip, short irqs);
286 int (*pre_read_config)(struct chip_t *chip, struct msgobj_t *obj);
287 int (*pre_write_config)(struct chip_t *chip, struct msgobj_t *obj,
288 struct canmsg_t *msg);
289 int (*send_msg)(struct chip_t *chip, struct msgobj_t *obj,
290 struct canmsg_t *msg);
291 int (*remote_request)(struct chip_t *chip, struct msgobj_t *obj);
292 int (*check_tx_stat)(struct chip_t *chip);
293 int (*wakeup_tx)(struct chip_t *chip, struct msgobj_t *obj);
294 int (*enable_configuration)(struct chip_t *chip);
295 int (*disable_configuration)(struct chip_t *chip);
296 int (*set_btregs)(struct chip_t *chip, unsigned short btr0,
297 unsigned short btr1);
298 int (*start_chip)(struct chip_t *chip);
299 int (*stop_chip)(struct chip_t *chip);
300 irqreturn_t (*irq_handler)(int irq, void *dev_id, struct pt_regs *regs);
305 struct mem_addr *next;
309 /* Structure for the RTR queue */
312 struct canmsg_t *rtr_message;
313 wait_queue_head_t rtr_wq;
318 extern int minor[MAX_TOT_CHIPS];
320 extern int baudrate[MAX_TOT_CHIPS];
321 extern char *hw[MAX_HW_CARDS];
322 extern int irq[MAX_IRQ];
323 extern unsigned long io[MAX_HW_CARDS];
324 extern int processlocal;
326 extern struct canhardware_t *hardware_p;
327 extern struct chip_t *chips_p[MAX_TOT_CHIPS];
328 extern struct msgobj_t *objects_p[MAX_TOT_MSGOBJS];
330 extern struct mem_addr *mem_head;
332 /* Inline function to write to the hardware registers. The argument address is
333 * relative to the memory map of the chip and not the absolute memory address.
335 extern inline void can_write_reg(const struct chip_t *chip, unsigned char data, unsigned address)
337 unsigned long address_to_write;
338 address_to_write = chip->chip_base_addr+address;
339 chip->write_register(data, address_to_write);
342 extern inline unsigned can_read_reg(const struct chip_t *chip, unsigned address)
344 unsigned long address_to_read;
345 address_to_read = chip->chip_base_addr+address;
346 return chip->read_register(address_to_read);
349 extern inline void canobj_write_reg(const struct chip_t *chip, const struct msgobj_t *obj,
350 unsigned char data, unsigned address)
352 unsigned long address_to_write;
353 address_to_write = obj->obj_base_addr+address;
354 chip->write_register(data, address_to_write);
357 extern inline unsigned canobj_read_reg(const struct chip_t *chip, const struct msgobj_t *obj,
360 unsigned long address_to_read;
361 address_to_read = obj->obj_base_addr+address;
362 return chip->read_register(address_to_read);
365 int can_base_addr_fixup(struct candevice_t *candev, unsigned long new_base);
366 int can_request_io_region(unsigned long start, unsigned long n, const char *name);
367 void can_release_io_region(unsigned long start, unsigned long n);
368 int can_request_mem_region(unsigned long start, unsigned long n, const char *name);
369 void can_release_mem_region(unsigned long start, unsigned long n);
372 const char *boardtype;
373 int (*board_register)(struct hwspecops_t *hwspecops);
377 const struct boardtype_t* boardtype_find(const char *str);