embedded/app/usbcan/sja1000p.c

   1 /**************************************************************************/
   2 /* File: sja1000p.c - Philips/NXP SJA1000 chip PeliCanCAN mode support    */
   3 /*                                                                        */
   4 /* LinCAN - (Not only) Linux CAN bus driver                               */
   5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz>   */
   6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz>             */
   7 /* Copyright (C) 2004-2005 Tomasz Motylewski (BFAD GmbH)                  */
   8 /* Funded by OCERA and FRESCOR IST projects                               */
   9 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl>      */
  10 /*                                                                        */
  11 /* LinCAN is free software; you can redistribute it and/or modify it      */
  12 /* under terms of the GNU General Public License as published by the      */
  13 /* Free Software Foundation; either version 2, or (at your option) any    */
  14 /* later version.  LinCAN is distributed in the hope that it will be      */
  15 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty    */
  16 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU    */
  17 /* General Public License for more details. You should have received a    */
  18 /* copy of the GNU General Public License along with LinCAN; see file     */
  19 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave,  */
  20 /* Cambridge, MA 02139, USA.                                              */
  21 /*                                                                        */
  22 /* To allow use of LinCAN in the compact embedded systems firmware        */
  23 /* and RT-executives (RTEMS for example), main authors agree with next    */
  24 /* special exception:                                                     */
  25 /*                                                                        */
  26 /* Including LinCAN header files in a file, instantiating LinCAN generics */
  27 /* or templates, or linking other files with LinCAN objects to produce    */
  28 /* an application image/executable, does not by itself cause the          */
  29 /* resulting application image/executable to be covered by                */
  30 /* the GNU General Public License.                                        */
  31 /* This exception does not however invalidate any other reasons           */
  32 /* why the executable file might be covered by the GNU Public License.    */
  33 /* Publication of enhanced or derived LinCAN files is required although.  */
  34 /**************************************************************************/
  35
  36 #include "./can/can.h"
  37 #include "./can/can_sysdep.h"
  38 #include "./can/main.h"
  39 #include "./can/sja1000p.h"
  40
  41 #ifdef CONFIG_OC_LINCAN_DETAILED_ERRORS
  42
  43 static const char *sja1000_ecc_errc_str[]={
  44         "bit error",
  45         "form error",
  46         "stuff error",
  47         "other type of error"
  48 };
  49
  50 static const char *sja1000_ecc_seg_str[]={
  51         "?0?",
  52         "?1?",
  53         "ID.28 to ID.21",
  54         "start of frame",
  55         "bit SRTR",
  56         "bit IDE",
  57         "ID.20 to ID.18",
  58         "ID.17 to ID.13",
  59         "CRC sequence",
  60         "reserved bit 0",
  61         "data field",
  62         "data length code",
  63         "bit RTR",
  64         "reserved bit 1",
  65         "ID.4 to ID.0",
  66         "ID.12 to ID.5",
  67         "?16?"
  68         "active error flag",
  69         "intermission",
  70         "tolerate dominant bits",
  71         "?20?",
  72         "?21?",
  73         "passive error flag",
  74         "error delimiter",
  75         "CRC delimiter",
  76         "acknowledge slot",
  77         "end of frame",
  78         "acknowledge delimiter",
  79         "overload flag",
  80         "?29?",
  81         "?30?",
  82         "?31?"
  83 };
  84
  85 #endif /*CONFIG_OC_LINCAN_DETAILED_ERRORS*/
  86
  87 static int sja1000_report_error_limit_counter;
  88
  89 static void sja1000_report_error(struct canchip_t *chip,
  90                                 unsigned sr, unsigned ir, unsigned ecc)
  91 {
  92         if(sja1000_report_error_limit_counter>=100)
  93                 return;
  94
  95         CANMSG("Error: status register: 0x%x irq_register: 0x%02x error: 0x%02x\n",
  96                 sr, ir, ecc);
  97
  98         sja1000_report_error_limit_counter+=10;
  99
 100         if(sja1000_report_error_limit_counter>=100){
 101                 sja1000_report_error_limit_counter+=10;
 102                 CANMSG("Error: too many errors, reporting disabled\n");
 103                 return;
 104         }
 105
 106 #ifdef CONFIG_OC_LINCAN_DETAILED_ERRORS
 107         CANMSG("SR: BS=%c  ES=%c  TS=%c  RS=%c  TCS=%c TBS=%c DOS=%c RBS=%c\n",
 108                 sr&sjaSR_BS?'1':'0',sr&sjaSR_ES?'1':'0',
 109                 sr&sjaSR_TS?'1':'0',sr&sjaSR_RS?'1':'0',
 110                 sr&sjaSR_TCS?'1':'0',sr&sjaSR_TBS?'1':'0',
 111                 sr&sjaSR_DOS?'1':'0',sr&sjaSR_RBS?'1':'0');
 112         CANMSG("IR: BEI=%c ALI=%c EPI=%c WUI=%c DOI=%c EI=%c  TI=%c  RI=%c\n",
 113                 sr&sjaIR_BEI?'1':'0',sr&sjaIR_ALI?'1':'0',
 114                 sr&sjaIR_EPI?'1':'0',sr&sjaIR_WUI?'1':'0',
 115                 sr&sjaIR_DOI?'1':'0',sr&sjaIR_EI?'1':'0',
 116                 sr&sjaIR_TI?'1':'0',sr&sjaIR_RI?'1':'0');
 117         if((sr&sjaIR_EI) || 1){
 118                 CANMSG("EI: %s %s %s\n",
 119                        sja1000_ecc_errc_str[(ecc&(sjaECC_ERCC1|sjaECC_ERCC0))/sjaECC_ERCC0],
 120                        ecc&sjaECC_DIR?"RX":"TX",
 121                        sja1000_ecc_seg_str[ecc&sjaECC_SEG_M]
 122                       );
 123         }
 124 #endif /*CONFIG_OC_LINCAN_DETAILED_ERRORS*/
 125 }
 126
 127
 128 /**
 129  * sja1000p_enable_configuration - enable chip configuration mode
 130  * @chip: pointer to chip state structure
 131  */
 132 int sja1000p_enable_configuration(struct canchip_t *chip)
 133 {
 134         int i=0;
 135         enum sja1000_PeliCAN_MOD flags;
 136
 137         can_disable_irq(chip->chip_irq);
 138
 139         flags=can_read_reg(chip,SJAMOD);
 140
 141         while ((!(flags & sjaMOD_RM)) && (i<=10)) {
 142                 can_write_reg(chip, sjaMOD_RM, SJAMOD);
 143 // TODO: configurable sjaMOD_AFM (32/16 bit acceptance filter)
 144 // config sjaMOD_LOM (listen only)
 145                 udelay(100);
 146                 i++;
 147                 flags=can_read_reg(chip, SJAMOD);
 148         }
 149         if (i>=10) {
 150                 CANMSG("Reset error\n");
 151                 can_enable_irq(chip->chip_irq);
 152                 return -ENODEV;
 153         }
 154
 155         return 0;
 156 }
 157
 158 /**
 159  * sja1000p_disable_configuration - disable chip configuration mode
 160  * @chip: pointer to chip state structure
 161  */
 162 int sja1000p_disable_configuration(struct canchip_t *chip)
 163 {
 164         int i=0;
 165         enum sja1000_PeliCAN_MOD flags;
 166
 167         flags=can_read_reg(chip,SJAMOD);
 168
 169         while ( (flags & sjaMOD_RM) && (i<=50) ) {
 170 // could be as long as 11*128 bit times after buss-off
 171                 can_write_reg(chip, 0, SJAMOD);
 172 // TODO: configurable sjaMOD_AFM (32/16 bit acceptance filter)
 173 // config sjaMOD_LOM (listen only)
 174                 udelay(100);
 175                 i++;
 176                 flags=can_read_reg(chip, SJAMOD);
 177         }
 178         if (i>=10) {
 179                 CANMSG("Error leaving reset status\n");
 180                 return -ENODEV;
 181         }
 182
 183         can_enable_irq(chip->chip_irq);
 184
 185         return 0;
 186 }
 187
 188 /**
 189  * sja1000p_chip_config: - can chip configuration
 190  * @chip: pointer to chip state structure
 191  *
 192  * This function configures chip and prepares it for message
 193  * transmission and reception. The function resets chip,
 194  * resets mask for acceptance of all messages by call to
 195  * sja1000p_extended_mask() function and then
 196  * computes and sets baudrate with use of function sja1000p_baud_rate().
 197  * Return Value: negative value reports error.
 198  * File: src/sja1000p.c
 199  */
 200 int sja1000p_chip_config(struct canchip_t *chip)
 201 {
 202         int i;
 203         unsigned char n, r;
 204
 205         if (sja1000p_enable_configuration(chip))
 206                 return -ENODEV;
 207
 208         /* Set mode, clock out, comparator */
 209         can_write_reg(chip,sjaCDR_PELICAN|chip->sja_cdr_reg,SJACDR);
 210
 211         /* Ensure, that interrupts are disabled even on the chip level now */
 212         can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER);
 213
 214         /* Set driver output configuration */
 215         can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
 216
 217         /* Simple check for chip presence */
 218         for (i=0, n=0x5a; i<8; i++, n+=0xf) {
 219                 can_write_reg(chip,n,SJAACR0+i);
 220         }
 221         for (i=0, n=0x5a; i<8; i++, n+=0xf) {
 222                 r = n^can_read_reg(chip,SJAACR0+i);
 223                 if (r) {
 224                         CANMSG("sja1000p_chip_config: chip connection broken,"
 225                                 " readback differ 0x%02x\n", r);
 226                         return -ENODEV;
 227                 }
 228         }
 229
 230
 231         if (sja1000p_extended_mask(chip,0x00000000, 0xffffffff))
 232                 return -ENODEV;
 233
 234         if (!chip->baudrate)
 235                 chip->baudrate=1000000;
 236         if (sja1000p_baud_rate(chip,chip->baudrate,chip->clock,0,75,0))
 237                 return -ENODEV;
 238
 239         /* Enable hardware interrupts */
 240         can_write_reg(chip, sjaENABLE_INTERRUPTS, SJAIER);
 241
 242         sja1000p_disable_configuration(chip);
 243
 244         return 0;
 245 }
 246
 247 /**
 248  * sja1000p_extended_mask: - setup of extended mask for message filtering
 249  * @chip: pointer to chip state structure
 250  * @code: can message acceptance code
 251  * @mask: can message acceptance mask
 252  *
 253  * Return Value: negative value reports error.
 254  * File: src/sja1000p.c
 255  */
 256 int sja1000p_extended_mask(struct canchip_t *chip, unsigned long code, unsigned  long mask)
 257 {
 258         int i;
 259
 260         if (sja1000p_enable_configuration(chip))
 261                 return -ENODEV;
 262
 263 // LSB to +3, MSB to +0
 264         for(i=SJA_PeliCAN_AC_LEN; --i>=0;) {
 265                 can_write_reg(chip,code&0xff,SJAACR0+i);
 266                 can_write_reg(chip,mask&0xff,SJAAMR0+i);
 267                 code >>= 8;
 268                 mask >>= 8;
 269         }
 270
 271         DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
 272         DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
 273
 274         sja1000p_disable_configuration(chip);
 275
 276         return 0;
 277 }
 278
 279 /**
 280  * sja1000p_baud_rate: - set communication parameters.
 281  * @chip: pointer to chip state structure
 282  * @rate: baud rate in Hz
 283  * @clock: frequency of sja1000 clock in Hz (ISA osc is 14318000)
 284  * @sjw: synchronization jump width (0-3) prescaled clock cycles
 285  * @sampl_pt: sample point in % (0-100) sets (TSEG1+1)/(TSEG1+TSEG2+2) ratio
 286  * @flags: fields %BTR1_SAM, %OCMODE, %OCPOL, %OCTP, %OCTN, %CLK_OFF, %CBP
 287  *
 288  * Return Value: negative value reports error.
 289  * File: src/sja1000p.c
 290  */
 291 int sja1000p_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
 292                                                         int sampl_pt, int flags)
 293 {
 294         int best_error = 1000000000, error;
 295         int best_tseg=0, best_brp=0, best_rate=0, brp=0;
 296         int tseg=0, tseg1=0, tseg2=0;
 297
 298         if (sja1000p_enable_configuration(chip))
 299                 return -ENODEV;
 300
 301         clock /=2;
 302
 303         /* tseg even = round down, odd = round up */
 304         for (tseg=(0+0+2)*2; tseg<=(sjaMAX_TSEG2+sjaMAX_TSEG1+2)*2+1; tseg++) {
 305                 brp = clock/((1+tseg/2)*rate)+tseg%2;
 306                 if (brp == 0 || brp > 64)
 307                         continue;
 308                 error = rate - clock/(brp*(1+tseg/2));
 309                 if (error < 0)
 310                         error = -error;
 311                 if (error <= best_error) {
 312                         best_error = error;
 313                         best_tseg = tseg/2;
 314                         best_brp = brp-1;
 315                         best_rate = clock/(brp*(1+tseg/2));
 316                 }
 317         }
 318         if (best_error && (rate/best_error < 10)) {
 319                 CANMSG("baud rate %d is not possible with %d Hz clock\n",
 320                                                                 rate, 2*clock);
 321                 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
 322                                 best_rate, best_brp, best_tseg, tseg1, tseg2);
 323                 return -EINVAL;
 324         }
 325         tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
 326         if (tseg2 < 0)
 327                 tseg2 = 0;
 328         if (tseg2 > sjaMAX_TSEG2)
 329                 tseg2 = sjaMAX_TSEG2;
 330         tseg1 = best_tseg-tseg2-2;
 331         if (tseg1>sjaMAX_TSEG1) {
 332                 tseg1 = sjaMAX_TSEG1;
 333                 tseg2 = best_tseg-tseg1-2;
 334         }
 335
 336         DEBUGMSG("Setting %d bps.\n", best_rate);
 337         DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
 338                                         best_brp, best_tseg, tseg1, tseg2,
 339                                         (100*(best_tseg-tseg2)/(best_tseg+1)));
 340
 341
 342         can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
 343         can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | (tseg2<<4)
 344                                         | tseg1, SJABTR1);
 345
 346         sja1000p_disable_configuration(chip);
 347
 348         return 0;
 349 }
 350
 351
 352 /**
 353  * sja1000p_set_bittiming: - set bittiming according to already computed parameters.
 354  * @chip: pointer to chip state structure
 355  * @bpr: baud rate prescaler
 356  * @sjw: synchronization jump width in bittime quanta
 357  * @tseg1: length of the segment 1 in bittime quanta
 358  * @tseg2: length of the segment 2 in bittime quanta
 359  *
 360  * Return Value: negative value reports error.
 361  * File: src/sja1000p.c
 362  */
 363 int sja1000p_set_bittiming(struct canchip_t *chip, int brp, int sjw, int tseg1, int tseg2)
 364 {
 365         uint8_t sam3times = 0; /* 0 = the bus is sampled once */
 366
 367         if((--brp)<0)
 368                 return -EINVAL;
 369
 370         if((--sjw)<0)
 371                 return -EINVAL;
 372
 373         if((--tseg1)<0)
 374                 return -EINVAL;
 375
 376         if((--tseg2)<0)
 377                 return -EINVAL;
 378
 379
 380
 381         if (sja1000p_enable_configuration(chip))
 382                 return -ENODEV;
 383
 384         can_write_reg(chip, sjw<<6 | brp, SJABTR0);
 385         can_write_reg(chip, (sam3times<<7) | (tseg2<<4) | tseg1, SJABTR1);
 386
 387         sja1000p_disable_configuration(chip);
 388
 389         return 0;
 390 }
 391
 392 /**
 393  * sja1000p_get_bittiming_const: - obtain description of chip bittiming calculation.
 394  * @chip: pointer to chip state structure
 395  * @btc: pointer to the structure filled by data
 396  *
 397  * Return Value: negative value reports error.
 398  * File: src/sja1000p.c
 399  */
 400 int sja1000p_get_bittiming_const(struct canchip_t *chip, struct can_bittiming_const *btc)
 401 {
 402         btc->tseg1_min = 1;
 403         btc->tseg1_max = 16; /* sjaMAX_TSEG1+1 */
 404         btc->tseg2_min = 1;
 405         btc->tseg2_max = 8; /* sjaMAX_TSEG2+1 */
 406         btc->sjw_max = 4;
 407         btc->brp_min = 1;
 408         btc->brp_max = 64;
 409         btc->brp_inc = 1;
 410
 411         return 0;
 412 }
 413
 414
 415 /**
 416  * sja1000p_read: - reads and distributes one or more received messages
 417  * @chip: pointer to chip state structure
 418  * @obj: pinter to CAN message queue information
 419  *
 420  * File: src/sja1000p.c
 421  */
 422 void sja1000p_read(struct canchip_t *chip, struct msgobj_t *obj) {
 423         int i, flags, len, datastart;
 424         do {
 425                 flags = can_read_reg(chip,SJAFRM);
 426                 if(flags&sjaFRM_FF) {
 427                         obj->rx_msg.id =
 428                                 (can_read_reg(chip,SJAID0)<<21) +
 429                                 (can_read_reg(chip,SJAID1)<<13) +
 430                                 (can_read_reg(chip,SJAID2)<<5) +
 431                                 (can_read_reg(chip,SJAID3)>>3);
 432                         datastart = SJADATE;
 433                 } else {
 434                         obj->rx_msg.id =
 435                                 (can_read_reg(chip,SJAID0)<<3) +
 436                                 (can_read_reg(chip,SJAID1)>>5);
 437                         datastart = SJADATS;
 438                 }
 439                 obj->rx_msg.flags =
 440                         ((flags & sjaFRM_RTR) ? MSG_RTR : 0) |
 441                         ((flags & sjaFRM_FF) ? MSG_EXT : 0);
 442                 len = flags & sjaFRM_DLC_M;
 443                 obj->rx_msg.length = len;
 444                 if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
 445                 for(i=0; i< len; i++) {
 446                         obj->rx_msg.data[i]=can_read_reg(chip,datastart+i);
 447                 }
 448
 449                 /* fill CAN message timestamp */
 450                 can_filltimestamp(&obj->rx_msg.timestamp);
 451
 452                 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
 453
 454                 can_write_reg(chip, sjaCMR_RRB, SJACMR);
 455
 456         } while (can_read_reg(chip, SJASR) & sjaSR_RBS);
 457 }
 458
 459 /**
 460  * sja1000p_pre_read_config: - prepares message object for message reception
 461  * @chip: pointer to chip state structure
 462  * @obj: pointer to message object state structure
 463  *
 464  * Return Value: negative value reports error.
 465  *      Positive value indicates immediate reception of message.
 466  * File: src/sja1000p.c
 467  */
 468 int sja1000p_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj)
 469 {
 470         int status;
 471         status=can_read_reg(chip,SJASR);
 472
 473         if(status  & sjaSR_BS) {
 474                 /* Try to recover from error condition */
 475                 DEBUGMSG("sja1000p_pre_read_config bus-off recover 0x%x\n",status);
 476                 sja1000p_enable_configuration(chip);
 477                 can_write_reg(chip, 0, SJARXERR);
 478                 can_write_reg(chip, 0, SJATXERR1);
 479                 can_read_reg(chip, SJAECC);
 480                 sja1000p_disable_configuration(chip);
 481         }
 482
 483         if (!(status&sjaSR_RBS)) {
 484                 return 0;
 485         }
 486
 487         can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER); //disable interrupts for a moment
 488         sja1000p_read(chip, obj);
 489         can_write_reg(chip, sjaENABLE_INTERRUPTS, SJAIER); //enable interrupts
 490         return 1;
 491 }
 492
 493 #define MAX_TRANSMIT_WAIT_LOOPS 10
 494 /**
 495  * sja1000p_pre_write_config: - prepares message object for message transmission
 496  * @chip: pointer to chip state structure
 497  * @obj: pointer to message object state structure
 498  * @msg: pointer to CAN message
 499  *
 500  * This function prepares selected message object for future initiation
 501  * of message transmission by sja1000p_send_msg() function.
 502  * The CAN message data and message ID are transfered from @msg slot
 503  * into chip buffer in this function.
 504  * Return Value: negative value reports error.
 505  * File: src/sja1000p.c
 506  */
 507 int sja1000p_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
 508                                                         struct canmsg_t *msg)
 509 {
 510         int i=0;
 511         unsigned int id;
 512         int status;
 513         int len;
 514
 515         /* Wait until Transmit Buffer Status is released */
 516         while ( !((status=can_read_reg(chip, SJASR)) & sjaSR_TBS) &&
 517                                                 i++<MAX_TRANSMIT_WAIT_LOOPS) {
 518                 udelay(i);
 519         }
 520
 521         if(status & sjaSR_BS) {
 522                 /* Try to recover from error condition */
 523                 DEBUGMSG("sja1000p_pre_write_config bus-off recover 0x%x\n",status);
 524                 sja1000p_enable_configuration(chip);
 525                 can_write_reg(chip, 0, SJARXERR);
 526                 can_write_reg(chip, 0, SJATXERR1);
 527                 can_read_reg(chip, SJAECC);
 528                 sja1000p_disable_configuration(chip);
 529         }
 530         if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
 531                 CANMSG("Transmit timed out, cancelling\n");
 532 // here we should check if there is no write/select waiting for this
 533 // transmit. If so, set error ret and wake up.
 534 // CHECKME: if we do not disable sjaIER_TIE (TX IRQ) here we get interrupt
 535 // immediately
 536                 can_write_reg(chip, sjaCMR_AT, SJACMR);
 537                 i=0;
 538                 while ( !(can_read_reg(chip, SJASR) & sjaSR_TBS) &&
 539                                                 i++<MAX_TRANSMIT_WAIT_LOOPS) {
 540                         udelay(i);
 541                 }
 542                 if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
 543                         CANMSG("Could not cancel, please reset\n");
 544                         return -EIO;
 545                 }
 546         }
 547         len = msg->length;
 548         if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
 549         /* len &= sjaFRM_DLC_M; ensured by above condition already */
 550         can_write_reg(chip, ((msg->flags&MSG_EXT)?sjaFRM_FF:0) |
 551                 ((msg->flags & MSG_RTR) ? sjaFRM_RTR : 0) | len, SJAFRM);
 552         if(msg->flags&MSG_EXT) {
 553                 id=msg->id<<3;
 554                 can_write_reg(chip, id & 0xff, SJAID3);
 555                 id >>= 8;
 556                 can_write_reg(chip, id & 0xff, SJAID2);
 557                 id >>= 8;
 558                 can_write_reg(chip, id & 0xff, SJAID1);
 559                 id >>= 8;
 560                 can_write_reg(chip, id, SJAID0);
 561                 for(i=0; i < len; i++) {
 562                         can_write_reg(chip, msg->data[i], SJADATE+i);
 563                 }
 564         } else {
 565                 id=msg->id<<5;
 566                 can_write_reg(chip, (id >> 8) & 0xff, SJAID0);
 567                 can_write_reg(chip, id & 0xff, SJAID1);
 568                 for(i=0; i < len; i++) {
 569                         can_write_reg(chip, msg->data[i], SJADATS+i);
 570                 }
 571         }
 572         return 0;
 573 }
 574
 575 /**
 576  * sja1000p_send_msg: - initiate message transmission
 577  * @chip: pointer to chip state structure
 578  * @obj: pointer to message object state structure
 579  * @msg: pointer to CAN message
 580  *
 581  * This function is called after sja1000p_pre_write_config() function,
 582  * which prepares data in chip buffer.
 583  * Return Value: negative value reports error.
 584  * File: src/sja1000p.c
 585  */
 586 int sja1000p_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
 587                                                         struct canmsg_t *msg)
 588 {
 589         can_write_reg(chip, sjaCMR_TR, SJACMR);
 590
 591         return 0;
 592 }
 593
 594 /**
 595  * sja1000p_check_tx_stat: - checks state of transmission engine
 596  * @chip: pointer to chip state structure
 597  *
 598  * Return Value: negative value reports error.
 599  *      Positive return value indicates transmission under way status.
 600  *      Zero value indicates finishing of all issued transmission requests.
 601  * File: src/sja1000p.c
 602  */
 603 int sja1000p_check_tx_stat(struct canchip_t *chip)
 604 {
 605         if (can_read_reg(chip,SJASR) & sjaSR_TCS)
 606                 return 0;
 607         else
 608                 return 1;
 609 }
 610
 611 /**
 612  * sja1000p_set_btregs: -  configures bitrate registers
 613  * @chip: pointer to chip state structure
 614  * @btr0: bitrate register 0
 615  * @btr1: bitrate register 1
 616  *
 617  * Return Value: negative value reports error.
 618  * File: src/sja1000p.c
 619  */
 620 int sja1000p_set_btregs(struct canchip_t *chip, unsigned short btr0,
 621                                                         unsigned short btr1)
 622 {
 623         if (sja1000p_enable_configuration(chip))
 624                 return -ENODEV;
 625
 626         can_write_reg(chip, btr0, SJABTR0);
 627         can_write_reg(chip, btr1, SJABTR1);
 628
 629         sja1000p_disable_configuration(chip);
 630
 631         return 0;
 632 }
 633
 634 /**
 635  * sja1000p_start_chip: -  starts chip message processing
 636  * @chip: pointer to chip state structure
 637  *
 638  * Return Value: negative value reports error.
 639  * File: src/sja1000p.c
 640  */
 641 int sja1000p_start_chip(struct canchip_t *chip)
 642 {
 643         enum sja1000_PeliCAN_MOD flags;
 644
 645         flags = can_read_reg(chip, SJAMOD) & (sjaMOD_LOM|sjaMOD_STM|sjaMOD_AFM|sjaMOD_SM);
 646         can_write_reg(chip, flags, SJAMOD);
 647
 648         sja1000_report_error_limit_counter=0;
 649
 650         return 0;
 651 }
 652
 653 /**
 654  * sja1000p_stop_chip: -  stops chip message processing
 655  * @chip: pointer to chip state structure
 656  *
 657  * Return Value: negative value reports error.
 658  * File: src/sja1000p.c
 659  */
 660 int sja1000p_stop_chip(struct canchip_t *chip)
 661 {
 662         enum sja1000_PeliCAN_MOD flags;
 663
 664         flags = can_read_reg(chip, SJAMOD) & (sjaMOD_LOM|sjaMOD_STM|sjaMOD_AFM|sjaMOD_SM);
 665         can_write_reg(chip, flags|sjaMOD_RM, SJAMOD);
 666
 667         return 0;
 668 }
 669
 670 /**
 671  * sja1000p_attach_to_chip: - attaches to the chip, setups registers and state
 672  * @chip: pointer to chip state structure
 673  *
 674  * Return Value: negative value reports error.
 675  * File: src/sja1000p.c
 676  */
 677 int sja1000p_attach_to_chip(struct canchip_t *chip)
 678 {
 679         return 0;
 680 }
 681
 682 /**
 683  * sja1000p_release_chip: - called before chip structure removal if %CHIP_ATTACHED is set
 684  * @chip: pointer to chip state structure
 685  *
 686  * Return Value: negative value reports error.
 687  * File: src/sja1000p.c
 688  */
 689 int sja1000p_release_chip(struct canchip_t *chip)
 690 {
 691         sja1000p_stop_chip(chip);
 692         can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER);
 693
 694         return 0;
 695 }
 696
 697 /**
 698  * sja1000p_remote_request: - configures message object and asks for RTR message
 699  * @chip: pointer to chip state structure
 700  * @obj: pointer to message object structure
 701  *
 702  * Return Value: negative value reports error.
 703  * File: src/sja1000p.c
 704  */
 705 int sja1000p_remote_request(struct canchip_t *chip, struct msgobj_t *obj)
 706 {
 707         CANMSG("sja1000p_remote_request not implemented\n");
 708         return -ENOSYS;
 709 }
 710
 711 /**
 712  * sja1000p_standard_mask: - setup of mask for message filtering
 713  * @chip: pointer to chip state structure
 714  * @code: can message acceptance code
 715  * @mask: can message acceptance mask
 716  *
 717  * Return Value: negative value reports error.
 718  * File: src/sja1000p.c
 719  */
 720 int sja1000p_standard_mask(struct canchip_t *chip, unsigned short code,
 721                 unsigned short mask)
 722 {
 723         CANMSG("sja1000p_standard_mask not implemented\n");
 724         return -ENOSYS;
 725 }
 726
 727 /**
 728  * sja1000p_clear_objects: - clears state of all message object residing in chip
 729  * @chip: pointer to chip state structure
 730  *
 731  * Return Value: negative value reports error.
 732  * File: src/sja1000p.c
 733  */
 734 int sja1000p_clear_objects(struct canchip_t *chip)
 735 {
 736         CANMSG("sja1000p_clear_objects not implemented\n");
 737         return -ENOSYS;
 738 }
 739
 740 /**
 741  * sja1000p_config_irqs: - tunes chip hardware interrupt delivery
 742  * @chip: pointer to chip state structure
 743  * @irqs: requested chip IRQ configuration
 744  *
 745  * Return Value: negative value reports error.
 746  * File: src/sja1000p.c
 747  */
 748 int sja1000p_config_irqs(struct canchip_t *chip, short irqs)
 749 {
 750         CANMSG("sja1000p_config_irqs not implemented\n");
 751         return -ENOSYS;
 752 }
 753
 754 /**
 755  * sja1000p_irq_write_handler: - part of ISR code responsible for transmit events
 756  * @chip: pointer to chip state structure
 757  * @obj: pointer to attached queue description
 758  *
 759  * The main purpose of this function is to read message from attached queues
 760  * and transfer message contents into CAN controller chip.
 761  * This subroutine is called by
 762  * sja1000p_irq_write_handler() for transmit events.
 763  * File: src/sja1000p.c
 764  */
 765 void sja1000p_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj)
 766 {
 767         int cmd;
 768
 769         if(obj->tx_slot){
 770                 /* Do local transmitted message distribution if enabled */
 771                 if (processlocal){
 772                         /* fill CAN message timestamp */
 773                         can_filltimestamp(&obj->tx_slot->msg.timestamp);
 774
 775                         obj->tx_slot->msg.flags |= MSG_LOCAL;
 776                         canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
 777                 }
 778                 /* Free transmitted slot */
 779                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 780                 obj->tx_slot=NULL;
 781         }
 782
 783         can_msgobj_clear_fl(obj,TX_PENDING);
 784         cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
 785         if(cmd<0)
 786                 return;
 787         can_msgobj_set_fl(obj,TX_PENDING);
 788
 789         if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
 790                 obj->ret = -1;
 791                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
 792                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 793                 obj->tx_slot=NULL;
 794                 return;
 795         }
 796         if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
 797                 obj->ret = -1;
 798                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
 799                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 800                 obj->tx_slot=NULL;
 801                 return;
 802         }
 803
 804 }
 805
 806 #define MAX_RETR 10
 807
 808 /**
 809  * sja1000p_irq_handler: - interrupt service routine
 810  * @irq: interrupt vector number, this value is system specific
 811  * @chip: pointer to chip state structure
 812  *
 813  * Interrupt handler is activated when state of CAN controller chip changes,
 814  * there is message to be read or there is more space for new messages or
 815  * error occurs. The receive events results in reading of the message from
 816  * CAN controller chip and distribution of message through attached
 817  * message queues.
 818  * File: src/sja1000p.c
 819  */
 820 int sja1000p_irq_handler(int irq, struct canchip_t *chip)
 821 {
 822         int irq_register, status, error_code;
 823         struct msgobj_t *obj=chip->msgobj[0];
 824         int loop_cnt=CHIP_MAX_IRQLOOP;
 825
 826         irq_register=can_read_reg(chip,SJAIR);
 827 //      DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
 828 //      DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
 829 //                                      can_read_reg(chip,SJASR));
 830
 831         if ((irq_register & (sjaIR_BEI|sjaIR_EPI|sjaIR_DOI|sjaIR_EI|sjaIR_TI|sjaIR_RI)) == 0)
 832                 return CANCHIP_IRQ_NONE;
 833
 834         if(!(chip->flags&CHIP_CONFIGURED)) {
 835                 CANMSG("sja1000p_irq_handler: called for non-configured device, irq_register 0x%02x\n", irq_register);
 836                 return CANCHIP_IRQ_NONE;
 837         }
 838
 839         status=can_read_reg(chip,SJASR);
 840
 841         do {
 842
 843                 if(!loop_cnt--) {
 844                         CANMSG("sja1000p_irq_handler IRQ %d stuck\n",irq);
 845                         return CANCHIP_IRQ_STUCK;
 846                 }
 847
 848                 /* (irq_register & sjaIR_RI) */
 849                 /*      old variant using SJAIR, collides with intended use with irq_accept */
 850                 if (status & sjaSR_RBS) {
 851                         DEBUGMSG("sja1000_irq_handler: RI or RBS\n");
 852                         sja1000p_read(chip,obj);
 853                         obj->ret = 0;
 854                 }
 855
 856                 /* (irq_register & sjaIR_TI) */
 857                 /*      old variant using SJAIR, collides with intended use with irq_accept */
 858                 if (((status & sjaSR_TBS) && can_msgobj_test_fl(obj,TX_PENDING))||
 859                     (can_msgobj_test_fl(obj,TX_REQUEST))) {
 860                         DEBUGMSG("sja1000_irq_handler: TI or TX_PENDING and TBS\n");
 861                         obj->ret = 0;
 862                         can_msgobj_set_fl(obj,TX_REQUEST);
 863                         while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
 864                                 can_msgobj_clear_fl(obj,TX_REQUEST);
 865
 866                                 if (can_read_reg(chip, SJASR) & sjaSR_TBS)
 867                                         sja1000p_irq_write_handler(chip, obj);
 868
 869                                 can_msgobj_clear_fl(obj,TX_LOCK);
 870                                 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
 871                                 DEBUGMSG("TX looping in sja1000_irq_handler\n");
 872                         }
 873                 }
 874                 if ((irq_register & (sjaIR_EI|sjaIR_BEI|sjaIR_EPI|sjaIR_DOI)) != 0) {
 875                         // Some error happened
 876                         error_code=can_read_reg(chip,SJAECC);
 877                         sja1000_report_error(chip, status, irq_register, error_code);
 878 // FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
 879 // Reset flag set to 0 if chip is already off the bus. Full state report
 880                         obj->ret=-1;
 881
 882                         if(error_code == 0xd9) {
 883                                 obj->ret= -ENXIO;
 884                                 /* no such device or address - no ACK received */
 885                         }
 886                         if(obj->tx_retry_cnt++>MAX_RETR) {
 887                                 can_write_reg(chip, sjaCMR_AT, SJACMR); // cancel any transmition
 888                                 obj->tx_retry_cnt = 0;
 889                         }
 890                         if(status&sjaSR_BS) {
 891                                 CANMSG("bus-off, resetting sja1000p\n");
 892                                 can_write_reg(chip, 0, SJAMOD);
 893                         }
 894
 895                         if(obj->tx_slot){
 896                                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_BUS);
 897                                 /*canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 898                                 obj->tx_slot=NULL;*/
 899                         }
 900
 901                 } else {
 902                         if(sja1000_report_error_limit_counter)
 903                                 sja1000_report_error_limit_counter--;
 904                         obj->tx_retry_cnt=0;
 905                 }
 906
 907                 irq_register=can_read_reg(chip,SJAIR);
 908
 909                 status=can_read_reg(chip,SJASR);
 910
 911                 if(((status & sjaSR_TBS) && can_msgobj_test_fl(obj,TX_PENDING)) ||
 912                    (irq_register & sjaIR_TI))
 913                          can_msgobj_set_fl(obj,TX_REQUEST);
 914
 915         } while((irq_register & (sjaIR_BEI|sjaIR_EPI|sjaIR_DOI|sjaIR_EI|sjaIR_RI)) ||
 916                 (can_msgobj_test_fl(obj,TX_REQUEST) && !can_msgobj_test_fl(obj,TX_LOCK)) ||
 917                 (status & sjaSR_RBS));
 918
 919         return CANCHIP_IRQ_HANDLED;
 920 }
 921
 922 /**
 923  * sja1000p_wakeup_tx: - wakeups TX processing
 924  * @chip: pointer to chip state structure
 925  * @obj: pointer to message object structure
 926  *
 927  * Function is responsible for initiating message transmition.
 928  * It is responsible for clearing of object TX_REQUEST flag
 929  *
 930  * Return Value: negative value reports error.
 931  * File: src/sja1000p.c
 932  */
 933 int sja1000p_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
 934 {
 935
 936         can_preempt_disable();
 937
 938         can_msgobj_set_fl(obj,TX_PENDING);
 939         can_msgobj_set_fl(obj,TX_REQUEST);
 940         while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
 941                 can_msgobj_clear_fl(obj,TX_REQUEST);
 942
 943                 if (can_read_reg(chip, SJASR) & sjaSR_TBS){
 944                         obj->tx_retry_cnt=0;
 945                         sja1000p_irq_write_handler(chip, obj);
 946                 }
 947
 948                 can_msgobj_clear_fl(obj,TX_LOCK);
 949                 if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
 950                 DEBUGMSG("TX looping in sja1000p_wakeup_tx\n");
 951         }
 952
 953         can_preempt_enable();
 954         return 0;
 955 }
 956
 957 int sja1000p_register(struct chipspecops_t *chipspecops)
 958 {
 959         CANMSG("initializing sja1000p chip operations\n");
 960         chipspecops->chip_config=sja1000p_chip_config;
 961         chipspecops->baud_rate=sja1000p_baud_rate;
 962         chipspecops->standard_mask=sja1000p_standard_mask;
 963         chipspecops->extended_mask=sja1000p_extended_mask;
 964         chipspecops->message15_mask=sja1000p_extended_mask;
 965         chipspecops->clear_objects=sja1000p_clear_objects;
 966         chipspecops->config_irqs=sja1000p_config_irqs;
 967         chipspecops->pre_read_config=sja1000p_pre_read_config;
 968         chipspecops->pre_write_config=sja1000p_pre_write_config;
 969         chipspecops->send_msg=sja1000p_send_msg;
 970         chipspecops->check_tx_stat=sja1000p_check_tx_stat;
 971         chipspecops->wakeup_tx=sja1000p_wakeup_tx;
 972         chipspecops->remote_request=sja1000p_remote_request;
 973         chipspecops->enable_configuration=sja1000p_enable_configuration;
 974         chipspecops->disable_configuration=sja1000p_disable_configuration;
 975         chipspecops->attach_to_chip=sja1000p_attach_to_chip;
 976         chipspecops->release_chip=sja1000p_release_chip;
 977         chipspecops->set_btregs=sja1000p_set_btregs;
 978         chipspecops->start_chip=sja1000p_start_chip;
 979         chipspecops->stop_chip=sja1000p_stop_chip;
 980         chipspecops->irq_handler=sja1000p_irq_handler;
 981         chipspecops->irq_accept=NULL;
 982         chipspecops->set_bittiming=sja1000p_set_bittiming;
 983         chipspecops->get_bittiming_const=sja1000p_get_bittiming_const;
 984         return 0;
 985 }
 986
 987 /**
 988  * sja1000p_fill_chipspecops - fills chip specific operations
 989  * @chip: pointer to chip representation structure
 990  *
 991  * The function fills chip specific operations for sja1000 (PeliCAN) chip.
 992  *
 993  * Return Value: returns negative number in the case of fail
 994  */
 995 int sja1000p_fill_chipspecops(struct canchip_t *chip)
 996 {
 997         chip->chip_type="sja1000p";
 998         chip->max_objects=1;
 999         sja1000p_register(chip->chipspecops);
1000         return 0;
1001 }