lincan/src/c_can.c

   1 /* c_can.c - Hynix HMS30c7202 ARM generic C_CAN module handling
   2  * Linux CAN-bus device driver.
   3  * Written by Sebastian Stolzenberg email:stolzi@sebastian-stolzenberg.de
   4  * Based on code from Arnaud Westenberg email:arnaud@wanadoo.nl
   5  * and Ake Hedman, eurosource, akhe@eurosource.se
   6  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
   7  * email:pisa@cmp.felk.cvut.cz
   8  * This software is released under the GPL-License.
   9  * Version lincan-0.3  17 Jun 2004
  10  */
  11
  12 #define __NO_VERSION__
  13
  14 #include "../include/can.h"
  15 #include "../include/can_sysdep.h"
  16 #include "../include/main.h"
  17 #include "../include/c_can.h"
  18
  19 extern int stdmask;
  20 extern int extmask;
  21
  22 can_spinlock_t c_can_spwlock=SPIN_LOCK_UNLOCKED; // Spin lock for write operations
  23 can_spinlock_t c_can_sprlock=SPIN_LOCK_UNLOCKED; // Spin lock for read operations
  24 can_spinlock_t c_can_if1lock=SPIN_LOCK_UNLOCKED; // spin lock for the if1 register
  25 can_spinlock_t c_can_if2lock=SPIN_LOCK_UNLOCKED; // spin lcok for the if2 register
  26
  27 /**
  28  * c_can_enable_configuration - enable chip configuration mode
  29  * @pchip: pointer to chip state structure
  30  */
  31 int c_can_enable_configuration(struct canchip_t *pchip)
  32 {
  33    int i=0;
  34    u16 flags;
  35    DEBUGMSG("(c%d)calling c_can_enable_configuration(...)\n", pchip->chip_idx);
  36 /*
  37    DEBUGMSG("Trying disable_irq(...) : ");
  38    //disable IRQ
  39         disable_irq(chip->chip_irq);
  40 */
  41    //read Control Register
  42    flags=c_can_read_reg_w(pchip, CCCR);
  43    //set Init-Bit in the Control Register (10 tries)
  44    while ((!(flags & CR_INIT)) && (i<=10))
  45      {
  46         c_can_write_reg_w(pchip,flags|CR_INIT, CCCR);
  47         udelay(1000);
  48         i++;
  49         flags=c_can_read_reg_w(pchip, CCCR);
  50      }
  51    if (i>=10)
  52      {
  53         CANMSG("Reset error\n");
  54         //enable_irq(chip->chip_irq);
  55         return -ENODEV;
  56      }
  57
  58    DEBUGMSG("-> ok\n");
  59    return 0;
  60 }
  61
  62 ///////////////////////////////////////////////////////////////////////
  63 int c_can_disable_configuration(struct canchip_t *pchip)
  64 {
  65    int i=0;
  66    u16 flags;
  67
  68    DEBUGMSG("(c%d)calling c_can_disable_configuration(...)\n", pchip->chip_idx);
  69    //read Control Register
  70    flags=c_can_read_reg_w(pchip, CCCR);
  71
  72    //reset Init-Bit in the Control Register (10 tries)
  73    while ( (flags & CR_INIT) && (i<=10) )
  74      {
  75         c_can_write_reg_w( pchip,flags & ~CR_INIT, CCCR);
  76         udelay(1000); //100 microseconds
  77         i++;
  78         flags=c_can_read_reg_w(pchip, CCCR);
  79      }
  80    if (i>=10)
  81      {
  82         CANMSG("Error leaving reset status\n");
  83         return -ENODEV;
  84      }
  85
  86    //enable IRQ
  87    //enable_irq(chip->chip_irq);
  88    DEBUGMSG("-> ok\n");
  89    return 0;
  90 }
  91
  92 ///////////////////////////////////////////////////////////////////////
  93 int c_can_chip_config(struct canchip_t *pchip)
  94 {
  95
  96    DEBUGMSG("(c%d)calling c_can_chip_config(...)\n", pchip->chip_idx);
  97    // Validate pointer
  98    if ( NULL == pchip ) return -1;
  99
 100    if (pchip->baudrate == 0)
 101      pchip->baudrate=1000;
 102
 103    if (c_can_baud_rate(pchip,pchip->baudrate*1000,pchip->clock,0,75,0))
 104      {
 105         CANMSG("Error configuring baud rate\n");
 106         return -ENODEV;
 107      }
 108         /*if (extended){
 109            if (c_can_extended_mask(pchip,0x0000000,extmask)) {
 110                    CANMSG("Error configuring extended mask\n");
 111                    return -ENODEV;
 112       }
 113    }else{
 114       if (c_can_standard_mask(pchip,0x0000,stdmask)) {
 115                    CANMSG("Error configuring standard mask\n");
 116                    return -ENODEV;
 117            }
 118         }*/
 119    if (c_can_clear_objects(pchip))
 120      {
 121         CANMSG("Error clearing message objects\n");
 122         return -ENODEV;
 123      }
 124    if (c_can_config_irqs(pchip, CR_MIE | CR_SIE | CR_EIE))
 125      {
 126         CANMSG("Error configuring interrupts\n");
 127         return -ENODEV;
 128      }
 129
 130    DEBUGMSG("-> Configured successfully\n");
 131
 132 #ifdef REGDUMP
 133    c_can_registerdump(pchip);
 134 #endif
 135
 136    return 0;
 137 }
 138
 139 ///////////////////////////////////////////////////////////////////////
 140 /*
 141  * Checks if the Busy-Bit in the IF1-Command-Request Register is set
 142  */
 143 int c_can_if1_busycheck(struct canchip_t *pchip)
 144 {
 145
 146    int i=0;
 147    unsigned short comreg = 0;
 148
 149    comreg = c_can_read_reg_w( pchip, CCIF1CR);
 150    while ( (comreg & IFXCR_BUSY) && (i<=10) )
 151      {
 152         udelay(100); //100 microseconds
 153         i++;
 154         comreg=c_can_read_reg_w( pchip, CCIF1CR);
 155      }
 156    if (i>=10)
 157      {
 158         CANMSG("Error Busy-Bit stays set\n");
 159         return -ENODEV;
 160      }
 161
 162    return 0;
 163 }
 164
 165 ///////////////////////////////////////////////////////////////////////
 166 /*
 167  * Checks if the Busy-Bit in the IF2-Command-Request Register is set
 168  */
 169 int c_can_if2_busycheck(struct canchip_t *pchip)
 170 {
 171
 172    int i=0;
 173    unsigned short comreg = 0;
 174
 175    comreg = c_can_read_reg_w( pchip, CCIF2CR);
 176    while ( (comreg & IFXCR_BUSY) && (i<=10) )
 177      {
 178         udelay(100); //100 microseconds
 179         i++;
 180         comreg=c_can_read_reg_w( pchip, CCIF2CR);
 181      }
 182    if (i>=10)
 183      {
 184         CANMSG("Error Busy-Bit stays set\n");
 185         return -ENODEV;
 186      }
 187
 188    return 0;
 189 }
 190
 191 ///////////////////////////////////////////////////////////////////////
 192 /*
 193  * Though the C-CAN Chip can handle one mask for each Message Object, this Method defines
 194  * one mask for all MOs. That means every MO gets the same mask.
 195  */
 196
 197 /* Set communication parameters.
 198  * param rate baud rate in Hz
 199  * param clock frequency of C-CAN clock in Hz
 200  * param sjw synchronization jump width (0-3) prescaled clock cycles
 201  * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
 202  * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
 203  */
 204 int c_can_baud_rate(struct canchip_t *pchip, int rate, int clock,
 205                         int sjw, int sampl_pt, int flags)
 206 {
 207    int best_error = 1000000000, error;
 208    int best_tseg=0, best_brp=0, best_rate=0, brp=0;
 209    int tseg=0, tseg1=0, tseg2=0;
 210
 211    unsigned short tempCR = 0;
 212
 213    DEBUGMSG("(c%d)calling c_can_baud_rate(...)\n", pchip->chip_idx);
 214
 215    if (c_can_enable_configuration(pchip))
 216      return -ENODEV;
 217
 218         /* tseg even = round down, odd = round up */
 219    for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++)
 220      {
 221         brp = clock/((1+tseg/2)*rate)+tseg%2;
 222         if (brp == 0 || brp > 64)
 223           continue;
 224         error = rate - clock/(brp*(1+tseg/2));
 225         if (error < 0)
 226           error = -error;
 227         if (error <= best_error)
 228           {
 229              best_error = error;
 230              best_tseg = tseg/2;
 231              best_brp = brp-1;
 232              best_rate = clock/(brp*(1+tseg/2));
 233           }
 234      }
 235    if (best_error && (rate/best_error < 10))
 236      {
 237         CANMSG("baud rate %d is not possible with %d Hz clock\n",
 238                rate, clock);
 239         CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
 240                best_rate, best_brp, best_tseg, tseg1, tseg2);
 241         return -EINVAL;
 242      }
 243    tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
 244    if (tseg2 < 0)
 245      tseg2 = 0;
 246    if (tseg2 > MAX_TSEG2)
 247      tseg2 = MAX_TSEG2;
 248    tseg1 = best_tseg-tseg2-2;
 249    if (tseg1 > MAX_TSEG1)
 250      {
 251         tseg1 = MAX_TSEG1;
 252         tseg2 = best_tseg-tseg1-2;
 253      }
 254
 255    DEBUGMSG("-> Setting %d bps.\n", best_rate);
 256    DEBUGMSG("->brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
 257             best_brp, best_tseg, tseg1, tseg2,
 258             (100*(best_tseg-tseg2)/(best_tseg+1)));
 259
 260    //read Control Register
 261    tempCR = c_can_read_reg_w( pchip, CCCR);
 262    //Configuration Change Enable
 263    c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
 264    c_can_write_reg_w(pchip, ((unsigned short)tseg2)<<12 | ((unsigned short)tseg1)<<8
 265                          | (unsigned short)sjw<<6 | (unsigned short) best_brp,
 266                          CCBT);
 267
 268    if (c_can_disable_configuration(pchip))
 269      return -ENODEV;
 270
 271    return 0;
 272 }
 273
 274 ///////////////////////////////////////////////////////////////////////
 275 int c_can_mask(struct msgobj_t *pmsgobj,
 276                u32 mask,
 277                u16 usedirbit)
 278 {
 279    unsigned short tempreg = 0;
 280    unsigned short readMaskCM;
 281    unsigned short writeMaskCM;
 282
 283    DEBUGMSG("(c%dm%d)calling c_can_mask(...)\n", pmsgobj->hostchip->chip_idx, pmsgobj->object);
 284
 285    readMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK;
 286    writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK | IFXCM_WRRD;
 287
 288    spin_lock( &c_can_if1lock );
 289
 290    //load Message Object in IF1
 291    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
 292    c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
 293    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 294
 295    //setting Message Valid Bit to zero
 296    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
 297    tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
 298    c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~(IFXARB2_MVAL), CCIF1A2);
 299    c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 300    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 301
 302    //setting UMask, MsgVal and Mask Register
 303    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
 304
 305    //writing acceptance mask for extended or standart mode
 306    if (can_msgobj_test_fl(pmsgobj,RX_MODE_EXT))
 307      {
 308         if (usedirbit)
 309           c_can_write_reg_w(pmsgobj->hostchip,
 310                             (mask>>16 & 0x1FFF) | IFXMSK2_MXTD | IFXMSK2_MDIR, CCIF1M2);
 311         else
 312           c_can_write_reg_w(pmsgobj->hostchip,
 313                             (mask>>16 & 0x1FFF) | IFXMSK2_MXTD, CCIF1M2);
 314         c_can_write_reg_w(pmsgobj->hostchip, (mask & 0xFFFF), CCIF1M1);
 315      }
 316    else
 317      {
 318         if (usedirbit)
 319           c_can_write_reg_w(pmsgobj->hostchip,
 320                             ((mask<<2) & 0x1FFC) | IFXMSK2_MDIR, CCIF1M2);
 321         else
 322           c_can_write_reg_w(pmsgobj->hostchip,
 323                             ((mask<<2) & 0x1FFC), CCIF1M2);
 324         c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1M1);
 325      }
 326    //seting Message Valid Bit to one
 327    tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
 328    c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
 329    //write to chip
 330    c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 331    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 332
 333    spin_unlock( &c_can_if1lock );
 334
 335    DEBUGMSG("-> Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
 336
 337 #ifdef REGDUMP
 338    c_can_registerdump(pmsgobj->hostchip);
 339 #endif
 340
 341    return 0;
 342 }
 343
 344 ///////////////////////////////////////////////////////////////////////
 345 int c_can_use_mask(struct msgobj_t *pmsgobj,
 346                    u16 useflag)
 347 {
 348    unsigned short tempreg = 0;
 349    unsigned short readMaskCM;
 350    unsigned short writeMaskCM;
 351
 352 #ifdef DEBUG
 353    char *boolstring = "false";
 354    if (useflag) boolstring = "true";
 355 #endif
 356    DEBUGMSG("(c%dm%d)calling c_can_use_mask(...)\n", pmsgobj->hostchip->chip_idx, pmsgobj->object);
 357
 358    readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
 359    writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;;
 360
 361    spin_lock( &c_can_if1lock );
 362
 363    //load Message Object in IF1
 364    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
 365    c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
 366    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 367
 368    //setting Message Valid Bit to zero
 369    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
 370    tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
 371    c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
 372    c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 373    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 374
 375    //setting UMask bit
 376    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
 377    if ( useflag )
 378      {
 379         tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
 380         c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXMC_UMASK, CCIF1DMC);
 381      }
 382    else
 383      {
 384         tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
 385         c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXMC_UMASK, CCIF1DMC);
 386      }
 387    //seting Message Valid Bit to one
 388    tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
 389    c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
 390    //write to chip
 391    c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 392    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 393
 394    spin_unlock( &c_can_if1lock );
 395
 396 #ifdef DEBUG
 397    DEBUGMSG("-> Setting umask bit to %s\n",boolstring);
 398 #endif
 399 #ifdef REGDUMP
 400    c_can_registerdump(pmsgobj->hostchip);
 401 #endif
 402
 403    return 0;
 404 }
 405
 406 ///////////////////////////////////////////////////////////////////////
 407 int c_can_clear_objects(struct canchip_t *pchip)
 408 {
 409    unsigned short i = 0;
 410    unsigned short tempreg = 0;
 411
 412    unsigned short maskCM = IFXCM_ARB;
 413
 414    DEBUGMSG("(c%d)calling c_can_clear_objects(...)\n", pchip->chip_idx);
 415
 416    spin_lock( &c_can_if1lock );
 417    spin_lock( &c_can_if2lock );
 418
 419    for (i=0; i<0x10; i++)
 420      {
 421
 422         //loading Message Objects in IF1 and IF2
 423         if (c_can_if1_busycheck(pchip)) return -ENODEV;
 424         c_can_write_reg_w(pchip, maskCM, CCIF1CM);
 425         c_can_write_reg_w(pchip, i, CCIF1CR);
 426         if (c_can_if2_busycheck(pchip)) return -ENODEV;
 427         c_can_write_reg_w(pchip, maskCM, CCIF2CM);
 428         c_can_write_reg_w(pchip, i+0x10, CCIF2CR);
 429
 430         //setting Message Valid Bit to zero
 431         if (c_can_if1_busycheck(pchip)) return -ENODEV;
 432         tempreg = c_can_read_reg_w(pchip, CCIF1A2);
 433         c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
 434         c_can_write_reg_w(pchip, i, CCIF1CR);
 435         if (c_can_if2_busycheck(pchip)) return -ENODEV;
 436         tempreg = c_can_read_reg_w(pchip, CCIF2A2);
 437         c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF2A2);
 438         c_can_write_reg_w(pchip, i+0x10, CCIF2CR);
 439      }
 440
 441    for (i=0; i<pchip->max_objects; i++)
 442      {
 443         if (can_msgobj_test_fl(pchip->msgobj[i],OPENED))
 444           {
 445              // In- and output buffer re-initialization
 446              canqueue_ends_flush_inlist(pchip->msgobj[i]->qends);
 447              canqueue_ends_flush_outlist(pchip->msgobj[i]->qends);
 448
 449           }
 450      }
 451
 452    spin_unlock( &c_can_if1lock );
 453    spin_unlock( &c_can_if2lock );
 454
 455    DEBUGMSG("-> Message Objects reset\n");
 456
 457    return 0;
 458 }
 459
 460 ///////////////////////////////////////////////////////////////////////
 461 int c_can_config_irqs(struct canchip_t *pchip,
 462                       u16 irqs)
 463 {
 464    u16 tempreg;
 465
 466    DEBUGMSG("(c%d)calling c_can_config_irqs(...)\n", pchip->chip_idx);
 467
 468    tempreg = c_can_read_reg_w(pchip, CCCR);
 469    DEBUGMSG("-> CAN Control Register: 0x%4lx\n",(long)tempreg);
 470    c_can_write_reg_w(pchip, tempreg | (irqs & 0xe), CCCR);
 471    DEBUGMSG("-> Configured hardware interrupt delivery\n");
 472    return 0;
 473 }
 474
 475 ///////////////////////////////////////////////////////////////////////
 476 int c_can_pre_read_config(struct canchip_t *pchip, struct msgobj_t *pmsgobj)
 477 {
 478    unsigned short readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
 479    unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
 480    unsigned short mcreg = 0;
 481    u32 id=pmsgobj->rx_preconfig_id;
 482
 483    DEBUGMSG("(c%dm%d)calling c_can_pre_read_config(...)\n", pmsgobj->hostchip->chip_idx, pmsgobj->object);
 484
 485    spin_lock( &c_can_if1lock );
 486
 487    if (c_can_if1_busycheck(pmsgobj->hostchip))
 488         goto error_enodev;
 489
 490    //loading Message Object in IF1
 491    c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
 492    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 493
 494    if (c_can_if1_busycheck(pmsgobj->hostchip))
 495         goto error_enodev;
 496
 497    //setting Message Valid Bit to zero
 498    c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A2);
 499    c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 500    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 501
 502    /* Only access when the C_CAN controller is idle */
 503    if (c_can_if1_busycheck(pmsgobj->hostchip))
 504         goto error_enodev;
 505
 506    //Configuring Message-Object
 507    mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
 508    c_can_write_reg_w(pmsgobj->hostchip,
 509                      ((mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_RXIE), CCIF1DMC);
 510
 511    //writing arbitration mask for extended or standart mode
 512    if (can_msgobj_test_fl(pmsgobj,RX_MODE_EXT))
 513      {
 514         c_can_write_reg_w(pmsgobj->hostchip,
 515                           IFXARB2_XTD | IFXARB2_MVAL | (id>>16 & 0x1FFF), CCIF1A2);
 516         c_can_write_reg_w(pmsgobj->hostchip, id & 0xFFFF, CCIF1A1);
 517      }
 518    else
 519      {
 520         c_can_write_reg_w(pmsgobj->hostchip,
 521                           IFXARB2_MVAL | (id<<2 & 0x1FFC), CCIF1A2);
 522         //c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
 523      }
 524    c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
 525    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 526
 527    spin_unlock( &c_can_if1lock );
 528
 529    DEBUGMSG("-> Receiving through message object %d with id=%d\n", pmsgobj->object,
 530             id);
 531 #ifdef REGDUMP
 532    c_can_registerdump(pmsgobj->hostchip);
 533 #endif
 534
 535    return 0;
 536
 537 error_enodev:
 538    CANMSG("Timeout in c_can_if1_busycheck\n");
 539    spin_unlock(&c_can_if1lock);
 540    return -ENODEV;
 541
 542 }
 543
 544 ///////////////////////////////////////////////////////////////////////
 545 int c_can_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
 546                                 struct canmsg_t *msg)
 547 {
 548         return 0;
 549 }
 550
 551  ///////////////////////////////////////////////////////////////////////
 552 /*
 553  *Prepare the Chip to send specified Message over specified Messageobject
 554  *In this version the method also sends the message.
 555  */
 556
 557 int c_can_send_msg(struct canchip_t *pchip, struct msgobj_t *pmsgobj,
 558                         struct canmsg_t *pmsg)
 559 {
 560    unsigned short readMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB;
 561    unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB| IFXCM_WRRD;
 562    unsigned short writeSendMskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB| IFXCM_WRRD | IFXCM_TRND;
 563    unsigned short mcreg = 0;
 564    //unsigned short arbreg = 0;
 565    unsigned short dataA1 = 0;
 566    unsigned short dataA2 = 0;
 567    unsigned short dataB1 = 0;
 568    unsigned short dataB2 = 0;
 569
 570    DEBUGMSG("(c%dm%d)calling c_can_send_msg(...)\n", pmsgobj->hostchip->chip_idx, pmsgobj->object);
 571
 572    spin_lock( &c_can_if2lock );
 573
 574    can_msgobj_clear_fl(pmsgobj,RX_MODE);
 575
 576    //loading Message Object in IF1
 577    if (c_can_if2_busycheck(pmsgobj->hostchip)) return -ENODEV;
 578    c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF2CM);
 579    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
 580    //setting Message Valid Bit to zero
 581    if (c_can_if2_busycheck(pmsgobj->hostchip)) return -ENODEV;
 582    c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF2A2);
 583    c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF2CM);
 584    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
 585    //Configuring MO
 586    if (c_can_if2_busycheck(pmsgobj->hostchip)) return -ENODEV;
 587    mcreg = c_can_read_reg_w( pmsgobj->hostchip, CCIF2CM);
 588    //remote enable?
 589    //define Command Mask
 590    c_can_write_reg_w(pmsgobj->hostchip, (mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_TXIE
 591                      | IFXMC_RMTEN | IFXMC_NEWDAT | IFXMC_TXRQST | (pmsg->length & 0xF), CCIF2DMC);
 592    //set Arbitration Bits
 593    if (can_msgobj_test_fl(pmsgobj,RX_MODE_EXT))
 594      {
 595         c_can_write_reg_w(pmsgobj->hostchip, (u16)(pmsg->id), CCIF2A1);
 596         c_can_write_reg_w(pmsgobj->hostchip, IFXARB2_XTD | IFXARB2_MVAL | IFXARB2_DIR
 597                                             | ((u16)(pmsg->id>>16) & 0x1FFF), CCIF2A2);
 598      }
 599    else
 600      {
 601         c_can_write_reg_w(pmsgobj->hostchip,
 602                           (IFXARB2_MVAL | IFXARB2_DIR | ((u16)(pmsg->id<<2) & 0x1FFC)), CCIF2A2);
 603         c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
 604      }
 605    //write Data
 606    if (pmsg->length>0)
 607      {
 608         dataA1 = pmsg->data[0] | (u16)pmsg->data[1]<<8;
 609         dataA2 = pmsg->data[2] | (u16)pmsg->data[3]<<8;
 610         dataB1 = pmsg->data[4] | (u16)pmsg->data[5]<<8;
 611         dataB2 = pmsg->data[6] | (u16)pmsg->data[7]<<8;
 612
 613         c_can_write_reg_w(pmsgobj->hostchip, dataA1, CCIF2DA1);
 614         c_can_write_reg_w(pmsgobj->hostchip, dataA2, CCIF2DA2);
 615         c_can_write_reg_w(pmsgobj->hostchip, dataB1, CCIF2DB1);
 616         c_can_write_reg_w(pmsgobj->hostchip, dataB2, CCIF2DB2);
 617      }
 618
 619    c_can_write_reg_w(pmsgobj->hostchip, writeSendMskCM, CCIF2CM);
 620    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
 621
 622    spin_unlock( &c_can_if2lock );
 623
 624    DEBUGMSG("-> ok\n");
 625 #ifdef REGDUMP
 626    c_can_registerdump(pmsgobj->hostchip);
 627 #endif
 628
 629    return 0;
 630 }
 631
 632 //////////////////////////////////////////////////////////////////////
 633 int c_can_remote_request(struct canchip_t *pchip, struct msgobj_t *pmsgobj )
 634 {
 635    unsigned short readMaskCM = IFXCM_CNTRL;// | IFXCM_ARB;
 636    //unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
 637    unsigned short mcreg = 0;
 638
 639    DEBUGMSG("(c%dm%d)calling c_can_remote_request(...)\n", pmsgobj->hostchip->chip_idx, pmsgobj->object);
 640
 641    //Remote request is only available when the message object is in receiving mode
 642    if (!can_msgobj_test_fl(pmsgobj,RX_MODE))
 643      {
 644         return 1;
 645      }
 646
 647    spin_lock( &c_can_if1lock );
 648
 649    //loading Message Object in IF1
 650    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
 651    c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
 652    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 653    //setting Transmit-Request-Bit
 654    if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
 655    mcreg = c_can_read_reg_w( pmsgobj->hostchip, CCIF1DMC);
 656    c_can_write_reg_w(pmsgobj->hostchip, mcreg | IFXMC_TXRQST, CCIF1DMC);
 657
 658    c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
 659
 660    spin_unlock( &c_can_if1lock );
 661
 662    DEBUGMSG("-> Sent remote request through message object %d\n", pmsgobj->object);
 663 #ifdef REGDUMP
 664    c_can_registerdump(pmsgobj->hostchip);
 665 #endif
 666
 667    return 0;
 668 }
 669
 670 ///////////////////////////////////////////////////////////////////////
 671 int c_can_set_btregs(struct canchip_t *pchip,
 672                      u16 btr0,
 673                      u16 btr1)
 674 {
 675    unsigned short tempCR = 0;
 676
 677    DEBUGMSG("(c%d)calling c_can_set_btregs(...)\n", pchip->chip_idx);
 678
 679    // Validate pointer
 680    if ( NULL == pchip ) return -1;
 681
 682    if (c_can_enable_configuration(pchip))
 683      return -ENODEV;
 684
 685    //read Control Register
 686    tempCR = c_can_read_reg_w(pchip, CCCR);
 687    //Configuration Change Enable
 688    c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
 689    c_can_write_reg_w(pchip, btr0 | (btr1<<8), CCBT);
 690
 691    if (c_can_disable_configuration(pchip))
 692      return -ENODEV;
 693
 694    DEBUGMSG("-> ok\n");
 695    return 0;
 696 }
 697
 698 ///////////////////////////////////////////////////////////////////////
 699 /*
 700  * Starts the Chip, by setting the CAN Enable Bit
 701  */
 702 int c_can_start_chip(struct canchip_t *pchip)
 703 {
 704    u16 flags = 0;
 705
 706    DEBUGMSG("(c%d)calling c_can_start_chip(...)\n", pchip->chip_idx);
 707
 708    // Validate pointer
 709    if ( NULL == pchip )
 710      {
 711         DEBUGMSG("-> Error Chip not available.\n");
 712         return -1;
 713      }
 714
 715 #ifdef C_CAN_WITH_CCCE
 716    flags = c_can_read_reg_w(pchip, CCCE) | CE_EN;
 717    c_can_write_reg_w(pchip, flags, CCCE);
 718 #endif
 719
 720    DEBUGMSG("-> ok\n");
 721 #ifdef REGDUMP
 722    c_can_registerdump(pchip);
 723 #endif
 724
 725    return 0;
 726 }
 727
 728 ///////////////////////////////////////////////////////////////////////
 729 /*
 730  * Stops the Chip, by deleting the CAN Enable Bit
 731  */
 732 int c_can_stop_chip(struct canchip_t *pchip)
 733 {
 734    u16 flags = 0;
 735
 736    DEBUGMSG("(c%d)calling c_can_stop_chip(...)\n", pchip->chip_idx);
 737
 738    // Validate pointer
 739    if ( NULL == pchip )
 740      {
 741         DEBUGMSG("-> Error Chip not available.\n");
 742         return -1;
 743      }
 744
 745 #ifdef C_CAN_WITH_CCCE
 746    flags = c_can_read_reg_w(pchip, CCCE) & ~CE_EN;
 747    c_can_write_reg_w(pchip, flags, CCCE);
 748 #endif
 749
 750    DEBUGMSG("-> ok\n");
 751    return 0;
 752 }
 753
 754 int c_can_attach_to_chip(struct canchip_t *chip)
 755 {
 756         return 0;
 757 }
 758
 759 int c_can_release_chip(struct canchip_t *chip)
 760 {
 761         int temp;
 762
 763         temp = c_can_read_reg_w(chip, CCCR);
 764
 765         /* Disable IRQ generation */
 766         c_can_config_irqs(chip, 0);
 767
 768         temp = c_can_read_reg_w(chip, CCCR);
 769
 770         /* Power-down C_CAN, except this does nothing in the version 1.2 */
 771         c_can_stop_chip(chip);
 772
 773
 774         return 0;
 775 }
 776
 777 ///////////////////////////////////////////////////////////////////////
 778 /*
 779  *Check the TxOK bit of the Status Register and resets it afterwards.
 780  */
 781 int c_can_check_tx_stat(struct canchip_t *pchip)
 782 {
 783    unsigned long tempstat = 0;
 784
 785    DEBUGMSG("(c%d)calling c_can_check_tx_stat(...)\n", pchip->chip_idx);
 786
 787    // Validate pointer
 788    if ( NULL == pchip ) return -1;
 789
 790    tempstat = c_can_read_reg_w(pchip, CCSR);
 791
 792    if (tempstat & SR_TXOK)
 793      {
 794         c_can_write_reg_w(pchip, tempstat & ~SR_TXOK, CCSR);
 795         return 0;
 796      }
 797    else
 798      {
 799         return 1;
 800      }
 801 }
 802
 803
 804 ///////////////////////////////////////////////////////////////////////
 805 int c_can_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
 806 {
 807         can_preempt_disable();
 808
 809         can_msgobj_set_fl(obj,TX_REQUEST);
 810
 811         /* calls i82527_irq_write_handler synchronized with other invocations
 812           from kernel and IRQ context */
 813         c_can_irq_sync_activities(chip, obj);
 814
 815         can_preempt_enable();
 816         return 0;
 817 }
 818
 819 ///////////////////////////////////////////////////////////////////////
 820 int c_can_filtch_rq(struct canchip_t *chip, struct msgobj_t *obj)
 821 {
 822         can_preempt_disable();
 823
 824         can_msgobj_set_fl(obj,FILTCH_REQUEST);
 825
 826         /* setups filter synchronized with other invocations from kernel and IRQ context */
 827         c_can_irq_sync_activities(chip, obj);
 828
 829         can_preempt_enable();
 830         return 0;
 831 }
 832
 833
 834 ///////////////////////////////////////////////////////////////////////
 835 void c_can_registerdump(struct canchip_t *pchip)
 836 {
 837    CANMSG("------------------------------------\n");
 838    CANMSG("---------C-CAN Register Dump--------\n");
 839    CANMSG("------------at 0x%.8lx-----------\n"
 840           ,(unsigned long)pchip->chip_base_addr);
 841    CANMSG("Control Register:             0x%.4lx\n",
 842           (long)(c_can_read_reg_w( pchip, CCCR)));
 843    CANMSG("Status Register:              0x%.4lx\n",
 844           (long)(c_can_read_reg_w( pchip, CCSR)));
 845    CANMSG("Error Counting Register:      0x%.4lx\n",
 846           (long)(c_can_read_reg_w( pchip, CCEC)));
 847    CANMSG("Bit Timing Register:          0x%.4lx\n",
 848           (long)(c_can_read_reg_w( pchip, CCBT)));
 849    CANMSG("Interrupt Register:           0x%.4lx\n",
 850           (long)(c_can_read_reg_w( pchip, CCINTR)));
 851    CANMSG("Test Register:                0x%.4lx\n",
 852           (long)(c_can_read_reg_w( pchip, CCTR)));
 853    CANMSG("Baud Rate Presc. Register:    0x%.4lx\n",
 854           (long)(c_can_read_reg_w( pchip, CCBRPE)));
 855 #ifdef C_CAN_WITH_CCCE
 856    CANMSG("CAN Enable Register:          0x%.4lx\n",
 857           (long)(c_can_read_reg_w( pchip, CCCE)));
 858 #endif
 859    CANMSG("Transm. Req. 1 Register:      0x%.4lx\n",
 860           (long)(c_can_read_reg_w( pchip, CCTREQ1)));
 861    CANMSG("Transm. Req. 2 Register:      0x%.4lx\n",
 862           (long)(c_can_read_reg_w( pchip, CCTREQ2)));
 863    CANMSG("New Data 1 Register:          0x%.4lx\n",
 864           (long)(c_can_read_reg_w( pchip, CCND1)));
 865    CANMSG("New Data 2 Register:          0x%.4lx\n",
 866           (long)(c_can_read_reg_w( pchip, CCND2)));
 867    CANMSG("Interrupt Pend. 1 Register:   0x%.4lx\n",
 868           (long)(c_can_read_reg_w( pchip, CCINTP1)));
 869    CANMSG("Interrupt Pend. 2 Register:   0x%.4lx\n",
 870           (long)(c_can_read_reg_w( pchip, CCINTP2)));
 871    CANMSG("------------------------------------\n");
 872    CANMSG("IF1 Command Req. Register:    0x%.4lx\n",
 873           (long)(c_can_read_reg_w( pchip, CCIF1CR)));
 874    CANMSG("IF1 Command Mask Register:    0x%.4lx\n",
 875           (long)(c_can_read_reg_w( pchip, CCIF1CM)));
 876    CANMSG("IF1 Mask 1 Register:          0x%.4lx\n",
 877           (long)(c_can_read_reg_w( pchip, CCIF1M1)));
 878    CANMSG("IF1 Mask 2 Register:          0x%.4lx\n",
 879           (long)(c_can_read_reg_w( pchip, CCIF1M2)));
 880    CANMSG("IF1 Arbitration 1 Register:   0x%.4lx\n",
 881           (long)(c_can_read_reg_w( pchip, CCIF1A1)));
 882    CANMSG("IF1 Arbitration 2 Register:   0x%.4lx\n",
 883           (long)(c_can_read_reg_w( pchip, CCIF1A2)));
 884    CANMSG("IF1 Message Control Register: 0x%.4lx\n",
 885           (long)(c_can_read_reg_w( pchip, CCIF1DMC)));
 886    CANMSG("IF1 Data A1 Register:         0x%.4lx\n",
 887           (long)(c_can_read_reg_w( pchip, CCIF1DA1)));
 888    CANMSG("IF1 Data A2 Register:         0x%.4lx\n",
 889           (long)(c_can_read_reg_w( pchip, CCIF1DA2)));
 890    CANMSG("IF1 Data B1 Register:         0x%.4lx\n",
 891           (long)(c_can_read_reg_w( pchip, CCIF1DB1)));
 892    CANMSG("IF1 Data B2 Register:         0x%.4lx\n",
 893           (long)(c_can_read_reg_w( pchip, CCIF1DB2)));
 894    CANMSG("------------------------------------\n");
 895    CANMSG("IF2 Command Req. Register:    0x%.4lx\n",
 896           (long)(c_can_read_reg_w( pchip, CCIF2CR)));
 897    CANMSG("IF2 Command Mask Register:    0x%.4lx\n",
 898           (long)(c_can_read_reg_w( pchip, CCIF2CM)));
 899    CANMSG("IF2 Mask 1 Register:          0x%.4lx\n",
 900           (long)(c_can_read_reg_w( pchip, CCIF2M1)));
 901    CANMSG("IF2 Mask 2 Register:          0x%.4lx\n",
 902           (long)(c_can_read_reg_w( pchip, CCIF2M2)));
 903    CANMSG("IF2 Arbitration 1 Register:   0x%.4lx\n",
 904           (long)(c_can_read_reg_w( pchip, CCIF2A1)));
 905    CANMSG("IF2 Arbitration 2 Register:   0x%.4lx\n",
 906           (long)(c_can_read_reg_w( pchip, CCIF2A2)));
 907    CANMSG("IF2 Message Control Register: 0x%.4lx\n",
 908           (long)(c_can_read_reg_w( pchip, CCIF2DMC)));
 909    CANMSG("IF2 Data A1 Register:         0x%.4lx\n",
 910           (long)(c_can_read_reg_w( pchip, CCIF2DA1)));
 911    CANMSG("IF2 Data A2 Register:         0x%.4lx\n",
 912           (long)(c_can_read_reg_w( pchip, CCIF2DA2)));
 913    CANMSG("IF2 Data B1 Register:         0x%.4lx\n",
 914           (long)(c_can_read_reg_w( pchip, CCIF2DB1)));
 915    CANMSG("IF2 Data B2 Register:         0x%.4lx\n",
 916           (long)(c_can_read_reg_w( pchip, CCIF2DB2)));
 917    CANMSG("------------------------------------\n");
 918    CANMSG("------------------------------------\n");
 919 }
 920
 921
 922 void c_can_if1_registerdump(struct canchip_t *pchip)
 923 {
 924    CANMSG("----------------------------------------\n");
 925    CANMSG("Error Counting Register:      0x%.4lx\n",
 926           (long)(c_can_read_reg_w( pchip, CCEC)));
 927    CANMSG("---------C-CAN IF1 Register Dump--------\n");
 928    CANMSG("IF1 Command Req. Register:    0x%.4lx\n",
 929           (long)(c_can_read_reg_w( pchip, CCIF1CR)));
 930    CANMSG("IF1 Command Mask Register:    0x%.4lx\n",
 931           (long)(c_can_read_reg_w( pchip, CCIF1CM)));
 932    CANMSG("IF1 Mask 1 Register:          0x%.4lx\n",
 933           (long)(c_can_read_reg_w( pchip, CCIF1M1)));
 934    CANMSG("IF1 Mask 2 Register:          0x%.4lx\n",
 935           (long)(c_can_read_reg_w( pchip, CCIF1M2)));
 936    CANMSG("IF1 Arbitration 1 Register:   0x%.4lx\n",
 937           (long)(c_can_read_reg_w( pchip, CCIF1A1)));
 938    CANMSG("IF1 Arbitration 2 Register:   0x%.4lx\n",
 939           (long)(c_can_read_reg_w( pchip, CCIF1A2)));
 940    CANMSG("IF1 Message Control Register: 0x%.4lx\n",
 941           (long)(c_can_read_reg_w( pchip, CCIF1DMC)));
 942    CANMSG("IF1 Data A1 Register:         0x%.4lx\n",
 943           (long)(c_can_read_reg_w( pchip, CCIF1DA1)));
 944    CANMSG("IF1 Data A2 Register:         0x%.4lx\n",
 945           (long)(c_can_read_reg_w( pchip, CCIF1DA2)));
 946    CANMSG("IF1 Data B1 Register:         0x%.4lx\n",
 947           (long)(c_can_read_reg_w( pchip, CCIF1DB1)));
 948    CANMSG("IF1 Data B2 Register:         0x%.4lx\n",
 949           (long)(c_can_read_reg_w( pchip, CCIF1DB2)));
 950 }
 951
 952 ///////////////////////////////////////////////////////////////////////
 953
 954 int c_can_register(struct chipspecops_t *chipspecops)
 955 {
 956         CANMSG("initializing c_can chip operations\n");
 957         chipspecops->chip_config=c_can_chip_config;
 958         chipspecops->baud_rate=c_can_baud_rate;
 959         /*chipspecops->standard_mask=c_can_standard_mask;
 960         chipspecops->extended_mask=c_can_extended_mask;
 961         chipspecops->message15_mask=c_can_extended_mask;*/
 962         chipspecops->clear_objects=c_can_clear_objects;
 963         /*chipspecops->config_irqs=c_can_config_irqs;*/
 964         chipspecops->pre_read_config=c_can_pre_read_config;
 965         chipspecops->pre_write_config=c_can_pre_write_config;
 966         chipspecops->send_msg=c_can_send_msg;
 967         chipspecops->check_tx_stat=c_can_check_tx_stat;
 968         chipspecops->wakeup_tx=c_can_wakeup_tx;
 969         chipspecops->filtch_rq = c_can_filtch_rq;
 970         chipspecops->remote_request=c_can_remote_request;
 971         chipspecops->enable_configuration=c_can_enable_configuration;
 972         chipspecops->disable_configuration=c_can_disable_configuration;
 973         chipspecops->attach_to_chip=c_can_attach_to_chip;
 974         chipspecops->release_chip=c_can_release_chip;
 975         chipspecops->set_btregs=c_can_set_btregs;
 976         chipspecops->start_chip=c_can_start_chip;
 977         chipspecops->stop_chip=c_can_stop_chip;
 978         chipspecops->irq_handler=c_can_irq_handler;
 979         chipspecops->irq_accept = NULL;
 980         return 0;
 981 }
 982
 983 int c_can_fill_chipspecops(struct canchip_t *chip)
 984 {
 985         chip->chip_type="c_can";
 986         if(MAX_MSGOBJS >= 32) {
 987                 chip->max_objects = 32;
 988         } else {
 989                 CANMSG("C_CAN requires 32 message objects per chip,"
 990                        " but only %d is compiled maximum\n",MAX_MSGOBJS);
 991                 chip->max_objects = MAX_MSGOBJS;
 992         }
 993         c_can_register(chip->chipspecops);
 994         return 0;
 995 }