embedded/board/arm/ul_usb1/libs/bspbase/bsp0hwinit.c

   1 #include "local_config.h"
   2 #include <system_def.h>
   3 #ifdef CONFIG_KEYVAL
   4   #include <keyvalpb.h>
   5   #include <lpciap.h>
   6   #include <lpciap_kvpb.h>
   7 #endif /* CONFIG_KEYVAL */
   8 #ifdef CONFIG_STDIO_COM_PORT
   9   #include <uart.h>
  10 #endif
  11 #ifdef CONFIG_OC_UL_DRV_SYSLESS
  12   #include <ul_lib/ulan.h>
  13   #include <string.h>
  14   #include <ul_drv_init.h>
  15   #include <ul_drv_iac.h>
  16   #include <ul_lib/ul_drvdef.h>
  17   extern long int uld_jiffies;
  18 #endif /* CONFIG_OC_UL_DRV_SYSLESS */
  19 #ifdef CONFIG_OC_I2C_DRV_SYSLESS
  20   #include <i2c_drv.h>
  21 #endif /* CONFIG_OC_I2C_DRV_SYSLESS */
  22 #ifdef CONFIG_OC_PBM_DRV
  23   #include <pbmcore.h>
  24   #include <pbm_8250.h>
  25   #include <pbm_drv_init.h>
  26 #endif /* CONFIG_OC_PBM_DRV */
  27 #include <hal_machperiph.h>
  28 #include <hal_intr.h>
  29
  30 /* timers */
  31 volatile lt_ticks_t sys_timer_ticks;
  32
  33 #ifdef CONFIG_OC_I2C_DRV_SYSLESS
  34 #define I2C_DRV_NA_MSTIMEOUT    10
  35 i2c_drv_t i2c_drv;
  36 int i2c_drv_na_timer=0;
  37 #endif /* CONFIG_OC_I2C_DRV_SYSLESS */
  38
  39 static void sysInit(void)
  40 {
  41
  42   system_clock_init();
  43
  44   // setup the parallel port pin
  45   IO0CLR = P0IO_ZERO_BITS;                // clear the ZEROs output
  46   IO0SET = P0IO_ONE_BITS;                 // set the ONEs output
  47   IO0DIR = P0IO_OUTPUT_BITS;              // set the output bit direction
  48
  49  #ifdef P1IO_OUTPUT_BITS
  50   IO1CLR = P1IO_ZERO_BITS;                // clear the ZEROs output
  51   IO1SET = P1IO_ONE_BITS;                 // set the ONEs output
  52   IO1DIR = P1IO_OUTPUT_BITS;              // set the output bit direction
  53  #endif
  54
  55   PINSEL1 = (PINSEL1 & 0x3FFFFFFF);
  56
  57   IO0CLR = LED1_BIT;                      // Indicate functional state on the LED1
  58 }
  59
  60 void timer0_isr(void)
  61 {
  62   unsigned int ir;
  63   ir=T0IR;
  64   if (ir&TIR_MR0I) {
  65     do {
  66       T0MR0+=PCLK/SYS_TIMER_HZ;
  67       T0IR=TIR_MR0I;               // Clear match0 interrupt
  68      #ifdef CONFIG_OC_UL_DRV_SYSLESS
  69       uld_jiffies++;
  70      #endif
  71      #ifdef CONFIG_OC_PBM_DRV
  72       pbm_jiffies++;
  73      #endif
  74      #ifdef CONFIG_OC_I2C_DRV_SYSLESS
  75       if (i2c_drv.flags&I2C_DRV_MS_INPR) {
  76         if (i2c_drv.flags&I2C_DRV_NA) {
  77           i2c_drv_na_timer++;
  78           if (i2c_drv_na_timer>I2C_DRV_NA_MSTIMEOUT) {
  79              if (i2c_drv.stroke_fnc)
  80               i2c_drv.stroke_fnc(&i2c_drv);
  81             i2c_drv_na_timer=0;
  82           }
  83         } else {
  84           i2c_drv_na_timer=0;
  85         }
  86         i2c_drv.flags|=I2C_DRV_NA;
  87       }
  88      #endif
  89       sys_timer_ticks++;
  90     } while (((int32_t)(T0MR0-T0TC))<0);
  91   }
  92 }
  93
  94 void timerInit(void)
  95 {
  96   sys_timer_ticks=0;
  97
  98   HAL_INTERRUPT_ATTACH(HAL_INTERRUPT_TIMER0,timer0_isr,0);
  99   HAL_INTERRUPT_UNMASK(HAL_INTERRUPT_TIMER0);
 100
 101   T0TC=0;
 102   T0MCR=0;
 103
 104   T0MR0=PCLK/SYS_TIMER_HZ;                            /* ms tics */
 105   T0MCR|=TMCR_MR0_I;
 106
 107   T0TCR = TCR_ENABLE; //Run timer 0
 108 }
 109
 110 #ifdef CONFIG_STDIO_COM_PORT
 111
 112 int uartcon_write(int file, const char * ptr, int len)
 113 {
 114   int cnt;
 115   unsigned char ch;
 116   for(cnt=0;cnt<len;cnt++,ptr++){
 117     ch=*ptr;
 118     if(ch==0xa)
 119       uart0Putch(0xd);
 120     uart0Putch(ch);
 121   }
 122   return cnt;
 123 }
 124
 125 void init_system_stub(void) {
 126   system_stub_ops.write=uartcon_write;
 127 }
 128
 129 #endif /* CONFIG_STDIO_COM_PORT */
 130
 131 #ifdef CONFIG_OC_UL_DRV_SYSLESS
 132
 133 extern unsigned uld_debug_flg; /* Left application  set defaults */
 134
 135 #ifndef CONFIG_KEYVAL
 136 unsigned long lpciap_buff[ISP_RAM2FLASH_BLOCK_SIZE/4];
 137 #endif /* CONFIG_KEYVAL */
 138
 139 #define UL_MTYPE_START32BIT 0x100
 140
 141 static inline int ul_iac_mem_head_rd(uint8_t *buf, int len,
 142                       uint32_t* pmtype, uint32_t* pstart, uint32_t* plen)
 143 {
 144   uint32_t val, mtype;
 145   if (len<6) return -1;
 146   mtype=*(buf++);       /* memory type */
 147   mtype+=*(buf++)<<8;
 148   val=*(buf++);           /* start address */
 149   val+=*(buf++)<<8;
 150   if(mtype&UL_MTYPE_START32BIT){
 151     if (len<8) return -1;
 152     val+=(uint32_t)*(buf++)<<16;
 153     val+=(uint32_t)*(buf++)<<24;
 154   }
 155   *pstart=val;
 156   val=*(buf++);           /* length */
 157   val+=*(buf++)<<8;
 158   if(mtype&UL_MTYPE_START32BIT){
 159     if (len==10) {
 160       val+=(uint32_t)*(buf++)<<16;
 161       val+=(uint32_t)*(buf++)<<24;
 162     }
 163   }
 164   *plen=val;
 165   mtype&=~UL_MTYPE_START32BIT;       /* 32-bit start address */
 166   *pmtype=mtype;
 167   return 0;
 168 }
 169
 170 int ul_iac_call_rdm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
 171 {
 172   uint32_t mtype,start,len;
 173
 174   data->len=0;
 175
 176   if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len))
 177     return UL_IAC_RC_PROC;
 178
 179   if (mtype==0x00) {
 180     data->len=len;
 181     data->buff=(char*)start;
 182     return UL_IAC_RC_FREEMSG;
 183   }
 184   return UL_IAC_RC_PROC;
 185 }
 186
 187 int ul_iac_call_erm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
 188 {
 189   uint32_t mtype,start,len;
 190
 191   data->len=0;
 192
 193   if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len))
 194     return UL_IAC_RC_PROC;
 195
 196  #ifdef CONFIG_KEYVAL
 197   if (mtype==0x01) {
 198     lpcisp_erase((void*)start,len);
 199     data->len=0;
 200     return UL_IAC_RC_FREEMSG;
 201   }
 202  #endif /* CONFIG_KEYVAL */
 203   return UL_IAC_RC_PROC;
 204 }
 205
 206 int ul_iac_call_wrm(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
 207 {
 208   uint32_t mtype,start,len;
 209
 210   data->len=0;
 211
 212   if(ul_iac_mem_head_rd((uint8_t *)ibuff, msginfo->len,&mtype,&start,&len))
 213     return UL_IAC_RC_PROC;
 214
 215   if (mtype==0x00) {
 216     memcpy((void*)start,data->buff,data->len);
 217     return UL_IAC_RC_FREEMSG;
 218   }
 219  #ifdef CONFIG_KEYVAL
 220   if (mtype==0x01) {
 221     lpcisp_write((char*)start, data->buff, ISP_RAM2FLASH_BLOCK_SIZE);
 222     return UL_IAC_RC_FREEMSG;
 223   }
 224  #endif /* CONFIG_KEYVAL */
 225   return UL_IAC_RC_PROC;
 226 }
 227
 228
 229 int ul_iac_call_deb(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
 230 {
 231   uint32_t debcmd,mtype,start;
 232   uint8_t *p=(uint8_t*)ibuff;
 233
 234   if (msginfo->len<1) return UL_IAC_RC_PROC;
 235   debcmd=*(p++);
 236   switch (debcmd) {
 237     case 0x10: /* goto */
 238       data->len=0;
 239       if (msginfo->len<5) return UL_IAC_RC_PROC;
 240       mtype=*(p++);
 241       mtype+=*(p++)<<8;
 242       start=*(p++);
 243       start+=*(p++)<<8;
 244       if(mtype&UL_MTYPE_START32BIT){
 245         mtype&=~UL_MTYPE_START32BIT;
 246         if (msginfo->len<7) return UL_IAC_RC_PROC;
 247         start+=(uint32_t)*(p++)<<16;
 248         start+=(uint32_t)*(p++)<<24;
 249       }
 250       if (mtype==0x00)
 251         ((void (*)())start)();
 252     default:break;
 253   }
 254   return UL_IAC_RC_PROC;
 255 }
 256
 257 int ul_iac_call_res(struct ul_drv *udrv,ul_msginfo *msginfo,char *ibuff,ul_iac_data *data)
 258 {
 259   uint32_t rescmd,pass;
 260   uint8_t *p=(uint8_t*)ibuff;
 261
 262   if (msginfo->len<1) return UL_IAC_RC_PROC;
 263   rescmd=*(p++);
 264   switch (rescmd) {
 265     case ULRES_CPU: /* CPU */
 266       data->len=0;
 267       if (msginfo->len<3) return UL_IAC_RC_PROC;
 268       pass=*(p++);
 269       pass+=*(p++)<<8;
 270       if (pass==0xaa55) {
 271         MEMMAP=MEMMAP_FLASH;
 272         lpc_watchdog_init(1,10); /* 10ms */
 273         lpc_watchdog_feed();
 274         while(1);
 275       }
 276     default:break;
 277   }
 278   return UL_IAC_RC_PROC;
 279 }
 280
 281 int uLanInit()
 282 {
 283   struct ul_drv *udrv;
 284
 285   /* set rs485 mode for UART1 */
 286   PINSEL0 = (PINSEL0 & ~0xFFFF0000) | 0x01550000; /* dsr(txd), cts(rxd), rts(rs485_dir), rxd, txd */
 287
 288   udrv=ul_drv_new(UL_DRV_SYSLESS_PORT,      /* port */
 289              UL_DRV_SYSLESS_IRQ,            /* irq */
 290              UL_DRV_SYSLESS_BAUD,           /* baud */
 291              UL_DRV_SYSLESS_MY_ADR_DEFAULT, /* my adr */
 292         #ifdef CONFIG_OC_UL_DRV_U450_VARPINS
 293           #if defined(CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG) && defined(CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP)
 294              "16450-dirneg-msrswap",        /* chip name */
 295           #elif defined(CONFIG_OC_UL_DRV_U450_VARPINS_MSRSWAP)
 296              "16450-msrswap",               /* chip name */
 297           #elif defined(CONFIG_OC_UL_DRV_U450_VARPINS_DIRNEG)
 298              "16450-dirneg",                /* chip name */
 299           #else
 300              "16450",                       /* chip name */
 301           #endif
 302         #else /*CONFIG_OC_UL_DRV_U450_VARPINS*/
 303              "16450",                       /* chip name */
 304         #endif /*CONFIG_OC_UL_DRV_U450_VARPINS*/
 305              0);                            /* baud base - default */
 306
 307   if (udrv==NULL)
 308     return -1;
 309
 310   ul_drv_add_iac(udrv,UL_CMD_RDM,UL_IAC_OP_SND,ul_iac_call_rdm,NULL,0,0,NULL,0);
 311   ul_drv_add_iac(udrv,UL_CMD_ERM,UL_IAC_OP_CALLBACK,ul_iac_call_erm,NULL,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
 312   ul_drv_add_iac(udrv,UL_CMD_WRM,UL_IAC_OP_REC,ul_iac_call_wrm,(char*)lpciap_buff,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
 313   ul_drv_add_iac(udrv,UL_CMD_DEB,UL_IAC_OP_CALLBACK,ul_iac_call_deb,NULL,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
 314   ul_drv_add_iac(udrv,UL_CMD_RES,UL_IAC_OP_CALLBACK,ul_iac_call_res,NULL,0,UL_IAC_BFL_CB_OFFLT,NULL,0);
 315
 316   return ul_drv_add_dev(udrv);
 317 }
 318 #endif /* CONFIG_OC_UL_DRV_SYSLESS */
 319
 320 #ifdef CONFIG_OC_I2C_DRV_SYSLESS
 321
 322 int
 323 i2cInit(void)
 324 {
 325
 326   /* set io pins */
 327  #if (I2C_DRV_SYSLESS_IRQ==9)
 328   PINSEL0 = (PINSEL0 & ~0x000000F0) | 0x00000050; /* I2C0 - SCL0, SDA0 */
 329  #elif (I2C_DRV_SYSLESS_IRQ==19)
 330   PINSEL0 = (PINSEL0 & ~0x30C00000) | 0x30C00000; /* I2C1 - SCL1, SDA1 */
 331  #else
 332    #error "wrong I2C pin maping!"
 333  #endif
 334
 335   if (i2c_drv_init(&i2c_drv,
 336                I2C_DRV_SYSLESS_PORT,
 337                I2C_DRV_SYSLESS_IRQ,
 338                I2C_DRV_SYSLESS_BITRATE,
 339                I2C_DRV_SYSLESS_SLADR)<0) return -1;
 340
 341   return 1;
 342 }
 343
 344 #endif /*CONFIG_OC_I2C_DRV_SYSLESS*/
 345
 346 #ifdef CONFIG_OC_PBM_DRV
 347
 348 void pbm_drv_init()
 349 {
 350         int rv = 0;
 351
 352         /* set rs485 mode for UART1 */
 353         /* dsr(txd), cts(rxd), rts(rs485_dir), rxd, txd */
 354         PINSEL0 = (PINSEL0 & ~0xFFFF0000) | 0x01550000;
 355
 356         PBMCHIP_INFO(PBMCHIP_DRV_DESCRIPTION ", "
 357                         PBMCHIP_DRV_VERSION ", "
 358                         PBMCHIP_DRV_COPYRIGHT "\n");
 359
 360         pbm_dev = pbm_alloc_dev(PBM_UART);
 361         if (!pbm_dev)
 362                 PBM_PRINT("unable to allocate device\n");
 363
 364         PBM_LOCK_INIT(&pbm_dev->lock);
 365         PBM_LOCK_INIT(&pbm_dev->irq_lock);
 366
 367         pbm_dev->node_res = &pbm_8250_res;
 368         pbm_8250_res.ioport = PBM_8250_PORT;
 369         pbm_8250_res.irq = PBM_8250_IRQ;
 370         PBMCHIP_INFO("port=0x%04x irq=%d\n",
 371                         pbm_8250_res.ioport, pbm_8250_res.irq);
 372
 373         /* disable all interrupts */
 374         pbm_outb(pbm_dev, UART_IER, 0x00);
 375
 376         /* get default parameters*/
 377         pbm_8250_get_params(pbm_dev, 0);
 378         /* chip operations and registering to pbmcore */
 379         pbm_dev->chops = chops;
 380         rv = pbm_register_chip(pbm_dev);
 381         if (rv)
 382                 PBM_PRINT("unable to register chip\n");
 383
 384         rv = request_irq(pbm_8250_res.irq, pbm_8250_intr, 0, "pbm_8250", pbm_dev);
 385
 386         pbm_8250_int_off_all(pbm_dev);
 387         pbm_8250_int_on_all(pbm_dev);
 388
 389         /* a hack to generate THRE interrupt on LPC2148 */
 390         pbm_outb(pbm_dev, UART_TX, 0x00);
 391 }
 392
 393 #endif /* CONFIG_OC_PBM_DRV */
 394
 395 void _setup_board()
 396 {
 397   // initialize the system
 398   sysInit();
 399
 400   #ifdef WATCHDOG_ENABLED
 401     lpc_watchdog_init(1,WATCHDOG_TIMEOUT_MS);
 402     lpc_watchdog_feed();
 403   #endif /* WATCHDOG_ENABLED */
 404
 405   // initialize the system timer
 406   timerInit();
 407
 408   #ifdef CONFIG_STDIO_COM_PORT
 409     uart0Init( B57600 , UART_8N1, UART_FIFO_8);
 410     init_system_stub();
 411   #endif /* CONFIG_STDIO_COM_PORT */
 412
 413   #ifdef CONFIG_OC_UL_DRV_SYSLESS
 414 //    uld_debug_flg=0x3ff;
 415     uLanInit();
 416   #endif /* CONFIG_OC_UL_DRV_SYSLESS */
 417
 418   #ifdef CONFIG_OC_I2C_DRV_SYSLESS
 419     i2cInit();
 420   #endif /* CONFIG_OC_I2C_DRV_SYSLESS */
 421
 422   #ifdef CONFIG_OC_PBM_DRV
 423     pbm_drv_init();
 424   #endif /* CONFIG_OC_PBM_DRV */
 425
 426 }