embedded/arch/arm/generic/defines/cpu_def.h

   1 #ifndef _ARM_CPU_DEF_H
   2 #define _ARM_CPU_DEF_H
   3
   4 #ifndef CODE
   5   #define CODE
   6 #endif
   7
   8 #ifndef XDATA
   9   #define XDATA
  10 #endif
  11
  12 #ifndef DATA
  13   #define DATA
  14 #endif
  15
  16 struct pt_regs {
  17         long uregs[18];
  18 };
  19
  20 #define ARM_cpsr        uregs[16]
  21 #define ARM_pc          uregs[15]
  22 #define ARM_lr          uregs[14]
  23 #define ARM_sp          uregs[13]
  24 #define ARM_ip          uregs[12]
  25 #define ARM_fp          uregs[11]
  26 #define ARM_r10         uregs[10]
  27 #define ARM_r9          uregs[9]
  28 #define ARM_r8          uregs[8]
  29 #define ARM_r7          uregs[7]
  30 #define ARM_r6          uregs[6]
  31 #define ARM_r5          uregs[5]
  32 #define ARM_r4          uregs[4]
  33 #define ARM_r3          uregs[3]
  34 #define ARM_r2          uregs[2]
  35 #define ARM_r1          uregs[1]
  36 #define ARM_r0          uregs[0]
  37 #define ARM_ORIG_r0     uregs[17]
  38
  39 struct undef_hook {
  40         struct undef_hook *next;
  41         unsigned long instr_mask;
  42         unsigned long instr_val;
  43         unsigned long cpsr_mask;
  44         unsigned long cpsr_val;
  45         int (*fn)(struct pt_regs *regs, unsigned int instr);
  46 };
  47
  48 int register_undef_hook(struct undef_hook *hook);
  49
  50 /* Low level CPU specific IRQ handling code */
  51
  52 #if !defined(__thumb__)
  53 /* Regular 32-bit ARM architecture */
  54
  55 #define WITH_IRQ_HANDLER_ARGS
  56
  57 #define sti()                                                   \
  58         ({                                                      \
  59                 unsigned long temp;                             \
  60         __asm__ __volatile__(                                   \
  61         "mrs    %0, cpsr                @ sti\n"                \
  62 "       bic     %0, %0, #128\n"                                 \
  63 "       msr     cpsr_c, %0"                                     \
  64         : "=r" (temp)                                           \
  65         :                                                       \
  66         : "memory", "cc");                                      \
  67         })
  68
  69 #define cli()                                                   \
  70         ({                                                      \
  71                 unsigned long temp;                             \
  72         __asm__ __volatile__(                                   \
  73         "mrs    %0, cpsr                @ cli\n"                \
  74 "       orr     %0, %0, #128\n"                                 \
  75 "       msr     cpsr_c, %0"                                     \
  76         : "=r" (temp)                                           \
  77         :                                                       \
  78         : "memory", "cc");                                      \
  79         })
  80
  81 #define save_and_cli(flags)                                     \
  82         ({                                                      \
  83                 unsigned long temp;                             \
  84                 (void) (&temp == &flags);                       \
  85         __asm__ __volatile__(                                   \
  86         "mrs    %0, cpsr                @ save_and_cli\n"       \
  87 "       orr     %1, %0, #128\n"                                 \
  88 "       msr     cpsr_c, %1"                                     \
  89         : "=r" (flags), "=r" (temp)                             \
  90         :                                                       \
  91         : "memory", "cc");                                      \
  92         })
  93
  94 #define save_flags(flags)                                       \
  95         ({                                                      \
  96         __asm__ __volatile__(                                   \
  97         "mrs    %0, cpsr                @ save_flags\n"         \
  98         : "=r" (flags)                                          \
  99         :                                                       \
 100         : "memory", "cc");                                      \
 101         })
 102
 103 #define restore_flags(flags)                                    \
 104         __asm__ __volatile__(                                   \
 105         "msr    cpsr_c, %0              @ restore_flags\n"      \
 106         :                                                       \
 107         : "r" (flags)                                           \
 108         : "memory", "cc")
 109
 110
 111 /* FIQ handling code */
 112
 113 #define fiq_sti()                                               \
 114         ({                                                      \
 115                 unsigned long temp;                             \
 116         __asm__ __volatile__(                                   \
 117         "mrs    %0, cpsr                @ sti\n"                \
 118 "       bic     %0, %0, #64\n"                                  \
 119 "       msr     cpsr_c, %0"                                     \
 120         : "=r" (temp)                                           \
 121         :                                                       \
 122         : "memory", "cc");                                      \
 123         })
 124
 125 #define fiq_cli()                                               \
 126         ({                                                      \
 127                 unsigned long temp;                             \
 128         __asm__ __volatile__(                                   \
 129         "mrs    %0, cpsr                @ cli\n"                \
 130 "       orr     %0, %0, #64\n"                                  \
 131 "       msr     cpsr_c, %0"                                     \
 132         : "=r" (temp)                                           \
 133         :                                                       \
 134         : "memory", "cc");                                      \
 135         })
 136
 137 #define fiq_save_and_cli(flags)                                 \
 138         ({                                                      \
 139                 unsigned long temp;                             \
 140                 (void) (&temp == &flags);                       \
 141         __asm__ __volatile__(                                   \
 142         "mrs    %0, cpsr                @ save_and_cli\n"       \
 143 "       orr     %1, %0, #192\n"                                 \
 144 "       msr     cpsr_c, %1"                                     \
 145         : "=r" (flags), "=r" (temp)                             \
 146         :                                                       \
 147         : "memory", "cc");                                      \
 148         })
 149
 150 #elif defined(__thumb2__) || defined (__ARM_ARCH_6M__)
 151 /* ARM Cortex-M3 architecture */
 152
 153 /* The interrupts are not delivered with argument,
 154    it is retrieved independent way - irq_arch_get_irqidx */
 155 #undef WITH_IRQ_HANDLER_ARGS
 156
 157 /* Offset between first interrupt source and exception table base */
 158 #define IRQ_IRQIDX_OFFSET 16
 159
 160 #define sti()                                                   \
 161         ({                                                      \
 162         __asm__ __volatile__(                                   \
 163         "cpsie  i                       @ sti\n"                \
 164         : : : "memory", "cc");                                  \
 165         })
 166
 167 #define cli()                                                   \
 168         ({                                                      \
 169         __asm__ __volatile__(                                   \
 170         "cpsid  i                       @ cli\n"                \
 171         : : : "memory", "cc");                                  \
 172         })
 173
 174 #define save_and_cli(flags)                                     \
 175         ({                                                      \
 176                 unsigned long temp;                             \
 177                 (void) (&temp == &flags);                       \
 178         __asm__ __volatile__(                                   \
 179         "mrs    %0, primask             @ save_and_cli\n"       \
 180 "       cpsid  i\n"                                             \
 181         : "=r" (flags)                                          \
 182         :                                                       \
 183         : "memory", "cc");                                      \
 184         })
 185
 186 #define save_flags(flags)                                       \
 187         ({                                                      \
 188                 unsigned long temp;                             \
 189                 (void) (&temp == &flags);                       \
 190         __asm__ __volatile__(                                   \
 191         "mrs    %0, primask             @ save_flags\n"         \
 192         : "=r" (flags)                                          \
 193         :                                                       \
 194         : "memory", "cc");                                      \
 195         })
 196
 197 #define restore_flags(flags)                                    \
 198         ({                                                      \
 199         __asm__ __volatile__(                                   \
 200         "msr    primask, %0            @ restore_flags\n"       \
 201         :                                                       \
 202         : "r" (flags)                                           \
 203         : "memory", "cc");                                      \
 204         })
 205
 206 #define irq_arch_get_irqidx()                                   \
 207         ({                                                      \
 208         unsigned long ipsr;                                     \
 209         __asm__ __volatile__(                                   \
 210         "mrs    %0, ipsr               @ get irqidx\n"          \
 211         : "=r" (ipsr) );                                        \
 212         ipsr;                                                   \
 213         })
 214
 215 #else /*defined(__thumb__)*/
 216
 217 #define WITH_IRQ_HANDLER_ARGS
 218 /* Regular ARM architecture in THUMB mode */
 219
 220 void irq_fnc_sti(void);
 221 #define sti irq_fnc_sti
 222 void irq_fnc_cli(void);
 223 #define cli irq_fnc_cli
 224 unsigned long irq_fnc_save_and_cli(void);
 225 #define save_and_cli(_flags) ((_flags)=irq_fnc_save_and_cli())
 226 unsigned long irq_fnc_save_flags(void);
 227 #define save_flags(_flags) ((_flags)=irq_fnc_save_flags())
 228 void irq_fnc_restore_flags(unsigned long flags);
 229 #define restore_flags irq_fnc_restore_flags
 230
 231 #endif /*defined(__thumb__)*/
 232
 233 void __cpu_coherent_range(unsigned long start, unsigned long end);
 234
 235 static inline void flush_icache_range(unsigned long start, unsigned long end)
 236 {
 237         __cpu_coherent_range(start, end);
 238 }
 239
 240 /* atomic access routines */
 241
 242 //typedef unsigned long atomic_t;
 243
 244 static inline void atomic_clear_mask(unsigned long mask, volatile unsigned long *addr)
 245 {
 246         unsigned long flags;
 247
 248         save_and_cli(flags);
 249         *addr &= ~mask;
 250         restore_flags(flags);
 251 }
 252
 253 static inline void atomic_set_mask(unsigned long mask, volatile unsigned long *addr)
 254 {
 255         unsigned long flags;
 256
 257         save_and_cli(flags);
 258         *addr |= mask;
 259         restore_flags(flags);
 260 }
 261
 262 static inline void set_bit(int nr, volatile unsigned long *addr)
 263 {
 264         unsigned long flags;
 265
 266         save_and_cli(flags);
 267         *addr |= 1<<nr;
 268         restore_flags(flags);
 269 }
 270
 271 static inline void clear_bit(int nr, volatile unsigned long *addr)
 272 {
 273         unsigned long flags;
 274
 275         save_and_cli(flags);
 276         *addr &= ~(1<<nr);
 277         restore_flags(flags);
 278 }
 279
 280 static inline int test_bit(int nr, volatile unsigned long *addr)
 281 {
 282         return ((*addr) & (1<<nr))?1:0;
 283 }
 284
 285 static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
 286 {
 287         unsigned long flags;
 288         long m=(1<<nr);
 289         long r;
 290
 291         save_and_cli(flags);
 292         r=*addr;
 293         *addr=r|m;
 294         restore_flags(flags);
 295         return r&m?1:0;
 296 }
 297
 298 #if defined(__thumb2__) || defined (__ARM_ARCH_6M__)
 299
 300 /* DMB, DSB, ISB */
 301
 302 #define __memory_barrier() \
 303  __asm__ __volatile__("dmb": : : "memory")
 304
 305 #else /* old plain ARM architecture */
 306
 307 #define __memory_barrier() \
 308  __asm__ __volatile__("": : : "memory")
 309
 310 #endif
 311
 312 /*masked fields macros*/
 313
 314 #define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
 315 #define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
 316
 317 static inline void outb(unsigned int port, int val) {
 318   *(volatile unsigned char *)(port)=val;
 319 }
 320
 321 static inline unsigned char inb(unsigned int port) {
 322   return *(volatile unsigned char *)(port);
 323 }
 324
 325 #define _WITHIN_CPU_DEF_H
 326 #include <irq_generic.h>
 327 #undef _WITHIN_CPU_DEF_H
 328
 329 extern void **irq_context_table;
 330 extern irq_handler_t **irq_handler_table;
 331 extern unsigned int irq_table_size;
 332
 333 /* Arithmetic functions */
 334 #if 0
 335 /* ARM v5E architecture - DSP extension */
 336
 337 #define sat_add_slsl(__x,__y) \
 338     __asm__ ("  qadd    %0,%0,%2\n" \
 339       : "=r"(__x) \
 340       : "0" ((long)__x), "r" ((long)__y) : "cc"); \
 341
 342 #define sat_sub_slsl(__x,__y) \
 343     __asm__ ("  qsub    %0,%0,%2\n" \
 344       : "=r"(__x) \
 345       : "0" ((long)__x), "r" ((long)__y) : "cc"); \
 346
 347 #elif !defined(__thumb__)
 348 /* Regular 32-bit ARM architecture */
 349
 350 #define sat_add_slsl(__x,__y) \
 351     __asm__ ("  adds    %0,%2\n" \
 352         "       eorvs   %0,%2,#0x80000000\n" \
 353         "       sbcvs   %0,%0,%2\n" \
 354       : "=r"(__x) \
 355       : "0" ((long)__x), "r" ((long)__y) : "cc"); \
 356
 357 #define sat_sub_slsl(__x,__y) \
 358     __asm__ ("  subs    %0,%2\n" \
 359         "       eorvs   %0,%2,#0x80000000\n" \
 360         "       sbcvs   %0,%0,%2\n" \
 361       : "=r"(__x) \
 362       : "0" ((long)__x), "r" ((long)__y) : "cc"); \
 363
 364 #elif defined(__thumb2__) || defined (__ARM_ARCH_6M__)
 365
 366 #define sat_add_slsl(__x,__y) \
 367     __asm__ ("  adds    %0,%2\n" \
 368         "       itt     vs\n" \
 369         "       eorsvs  %0,%3,%2\n" \
 370         "       sbcsvs  %0,%0,%2\n" \
 371       : "=r"(__x) \
 372       : "0" ((long)__x), "r" ((long)__y), "r" (0x80000000): "cc"); \
 373
 374 #define sat_sub_slsl(__x,__y) \
 375     __asm__ ("  subs    %0,%2\n" \
 376         "       itt     vs\n" \
 377         "       eorsvs  %0,%3,%2\n" \
 378         "       sbcsvs  %0,%0,%2\n" \
 379       : "=r"(__x) \
 380       : "0" ((long)__x), "r" ((long)__y), "r" (0x80000000) : "cc"); \
 381
 382 #endif
 383
 384 #endif /* _ARM_CPU_DEF_H */