lincan/src/sja1000p.c

   1 /* sja1000.c
   2  * Linux CAN-bus device driver.
   3  * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
   4  * Changed for PeliCan mode SJA1000 by Tomasz Motylewski (BFAD GmbH)
   5  * T.Motylewski@bfad.de
   6  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
   7  * email:pisa@cmp.felk.cvut.cz
   8  * This software is released under the GPL-License.
   9  * Version lincan-0.2  9 Jul 2003
  10  */
  11
  12 #include <linux/autoconf.h>
  13
  14 #include <linux/sched.h>
  15 #include <linux/delay.h>
  16 #include <asm/irq.h>
  17
  18 #include "../include/main.h"
  19 #include "../include/sja1000p.h"
  20
  21 int sja1000p_enable_configuration(struct chip_t *chip)
  22 {
  23         int i=0;
  24         enum sja1000_PeliCAN_MOD flags;
  25
  26         disable_irq(chip->chip_irq);
  27
  28         flags=can_read_reg(chip,SJAMOD);
  29
  30         while ((!(flags & MOD_RM)) && (i<=10)) {
  31                 can_write_reg(chip, MOD_RM, SJAMOD);
  32 // TODO: configurable MOD_AFM (32/16 bit acceptance filter)
  33 // config MOD_LOM (listen only)
  34                 udelay(100);
  35                 i++;
  36                 flags=can_read_reg(chip, SJAMOD);
  37         }
  38         if (i>=10) {
  39                 CANMSG("Reset error\n");
  40                 enable_irq(chip->chip_irq);
  41                 return -ENODEV;
  42         }
  43
  44         return 0;
  45 }
  46
  47 int sja1000p_disable_configuration(struct chip_t *chip)
  48 {
  49         int i=0;
  50         enum sja1000_PeliCAN_MOD flags;
  51
  52         flags=can_read_reg(chip,SJAMOD);
  53
  54         while ( (flags & MOD_RM) && (i<=50) ) {
  55 // could be as long as 11*128 bit times after buss-off
  56                 can_write_reg(chip, 0, SJAMOD);
  57 // TODO: configurable MOD_AFM (32/16 bit acceptance filter)
  58 // config MOD_LOM (listen only)
  59                 udelay(100);
  60                 i++;
  61                 flags=can_read_reg(chip, SJAMOD);
  62         }
  63         if (i>=10) {
  64                 CANMSG("Error leaving reset status\n");
  65                 return -ENODEV;
  66         }
  67
  68         enable_irq(chip->chip_irq);
  69
  70         return 0;
  71 }
  72
  73 /**
  74  * sja1000p_chip_config: - can chip configuration
  75  * @chip: pointer to chip state structure
  76  *
  77  * This function configures chip and prepares it for message
  78  * transmission and reception. The function resets chip,
  79  * resets mask for acceptance of all messages by call to
  80  * sja1000p_extended_mask() function and then
  81  * computes and sets baudrate with use of function sja1000p_baud_rate().
  82  * Return Value: negative value reports error.
  83  * File: src/sja1000p.c
  84  */
  85 int sja1000p_chip_config(struct chip_t *chip)
  86 {
  87         if (sja1000p_enable_configuration(chip))
  88                 return -ENODEV;
  89
  90         /* Set mode, clock out, comparator */
  91         can_write_reg(chip,CDR_PELICAN|chip->sja_cdr_reg,SJACDR);
  92         /* Set driver output configuration */
  93         can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
  94
  95         if (sja1000p_extended_mask(chip,0x00000000, 0xffffffff))
  96                 return -ENODEV;
  97
  98         if (!baudrate)
  99                 baudrate=1000;
 100         if (sja1000p_baud_rate(chip,1000*baudrate,chip->clock,0,75,0))
 101                 return -ENODEV;
 102
 103         /* Enable hardware interrupts */
 104         can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER);
 105
 106         sja1000p_disable_configuration(chip);
 107
 108         return 0;
 109 }
 110
 111 /**
 112  * sja1000p_extended_mask: - setup of extended mask for message filtering
 113  * @chip: pointer to chip state structure
 114  * @code: can message acceptance code
 115  * @mask: can message acceptance mask
 116  *
 117  * Return Value: negative value reports error.
 118  * File: src/sja1000p.c
 119  */
 120 int sja1000p_extended_mask(struct chip_t *chip, unsigned long code, unsigned  long mask)
 121 {
 122         int i;
 123
 124         if (sja1000p_enable_configuration(chip))
 125                 return -ENODEV;
 126
 127 // LSB to +3, MSB to +0
 128         for(i=SJA_PeliCAN_AC_LEN; --i>=0;) {
 129                 can_write_reg(chip,code&0xff,SJAACR0+i);
 130                 can_write_reg(chip,mask&0xff,SJAAMR0+i);
 131                 code >>= 8;
 132                 mask >>= 8;
 133         }
 134
 135         DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
 136         DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
 137
 138         sja1000p_disable_configuration(chip);
 139
 140         return 0;
 141 }
 142
 143 /**
 144  * sja1000p_baud_rate: - set communication parameters.
 145  * @chip: pointer to chip state structure
 146  * @rate: baud rate in Hz
 147  * @clock: frequency of sja1000 clock in Hz (ISA osc is 14318000)
 148  * @sjw: synchronization jump width (0-3) prescaled clock cycles
 149  * @sampl_pt: sample point in % (0-100) sets (TSEG1+1)/(TSEG1+TSEG2+2) ratio
 150  * @flags: fields %BTR1_SAM, %OCMODE, %OCPOL, %OCTP, %OCTN, %CLK_OFF, %CBP
 151  *
 152  * Return Value: negative value reports error.
 153  * File: src/sja1000p.c
 154  */
 155 int sja1000p_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
 156                                                         int sampl_pt, int flags)
 157 {
 158         int best_error = 1000000000, error;
 159         int best_tseg=0, best_brp=0, best_rate=0, brp=0;
 160         int tseg=0, tseg1=0, tseg2=0;
 161
 162         if (sja1000p_enable_configuration(chip))
 163                 return -ENODEV;
 164
 165         clock /=2;
 166
 167         /* tseg even = round down, odd = round up */
 168         for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
 169                 brp = clock/((1+tseg/2)*rate)+tseg%2;
 170                 if (brp == 0 || brp > 64)
 171                         continue;
 172                 error = rate - clock/(brp*(1+tseg/2));
 173                 if (error < 0)
 174                         error = -error;
 175                 if (error <= best_error) {
 176                         best_error = error;
 177                         best_tseg = tseg/2;
 178                         best_brp = brp-1;
 179                         best_rate = clock/(brp*(1+tseg/2));
 180                 }
 181         }
 182         if (best_error && (rate/best_error < 10)) {
 183                 CANMSG("baud rate %d is not possible with %d Hz clock\n",
 184                                                                 rate, 2*clock);
 185                 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
 186                                 best_rate, best_brp, best_tseg, tseg1, tseg2);
 187                 return -EINVAL;
 188         }
 189         tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
 190         if (tseg2 < 0)
 191                 tseg2 = 0;
 192         if (tseg2 > MAX_TSEG2)
 193                 tseg2 = MAX_TSEG2;
 194         tseg1 = best_tseg-tseg2-2;
 195         if (tseg1>MAX_TSEG1) {
 196                 tseg1 = MAX_TSEG1;
 197                 tseg2 = best_tseg-tseg1-2;
 198         }
 199
 200         DEBUGMSG("Setting %d bps.\n", best_rate);
 201         DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
 202                                         best_brp, best_tseg, tseg1, tseg2,
 203                                         (100*(best_tseg-tseg2)/(best_tseg+1)));
 204
 205
 206         can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
 207         can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | (tseg2<<4)
 208                                         | tseg1, SJABTR1);
 209
 210         sja1000p_disable_configuration(chip);
 211
 212         return 0;
 213 }
 214
 215 /**
 216  * sja1000p_read: - reads and distributes one or more received messages
 217  * @chip: pointer to chip state structure
 218  * @obj: pinter to CAN message queue information
 219  *
 220  * File: src/sja1000p.c
 221  */
 222 void sja1000p_read(struct chip_t *chip, struct msgobj_t *obj) {
 223         int i, flags, len, datastart;
 224         do {
 225                 flags = can_read_reg(chip,SJAFRM);
 226                 if(flags&FRM_FF) {
 227                         obj->rx_msg.id =
 228                                 (can_read_reg(chip,SJAID0)<<21) +
 229                                 (can_read_reg(chip,SJAID1)<<13) +
 230                                 (can_read_reg(chip,SJAID2)<<5) +
 231                                 (can_read_reg(chip,SJAID3)>>3);
 232                         datastart = SJADATE;
 233                 } else {
 234                         obj->rx_msg.id =
 235                                 (can_read_reg(chip,SJAID0)<<3) +
 236                                 (can_read_reg(chip,SJAID1)>>5);
 237                         datastart = SJADATS;
 238                 }
 239                 obj->rx_msg.flags =
 240                         ((flags & FRM_RTR) ? MSG_RTR : 0) |
 241                         ((flags & FRM_FF) ? MSG_EXT : 0);
 242                 len = flags & FRM_DLC_M;
 243                 for(i=0; i< len; i++) {
 244                         obj->rx_msg.data[i]=can_read_reg(chip,datastart+i);
 245                 }
 246                 obj->rx_msg.length = len;
 247
 248                 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
 249
 250                 can_write_reg(chip, CMR_RRB, SJACMR);
 251
 252         } while (can_read_reg(chip, SJASR) & SR_RBS);
 253 }
 254
 255 /**
 256  * sja1000p_pre_read_config: - prepares message object for message reception
 257  * @chip: pointer to chip state structure
 258  * @obj: pointer to message object state structure
 259  *
 260  * Return Value: negative value reports error.
 261  *      Positive value indicates immediate reception of message.
 262  * File: src/sja1000p.c
 263  */
 264 int sja1000p_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
 265 {
 266         int status;
 267         status=can_read_reg(chip,SJASR);
 268
 269         if(status  & SR_BS) {
 270                 /* Try to recover from error condition */
 271                 DEBUGMSG("sja1000p_pre_read_config bus-off recover 0x%x\n",status);
 272                 sja1000p_enable_configuration(chip);
 273                 can_write_reg(chip, 0, SJARXERR);
 274                 can_write_reg(chip, 0, SJATXERR1);
 275                 can_read_reg(chip, SJAECC);
 276                 sja1000p_disable_configuration(chip);
 277         }
 278
 279         if (!(status&SR_RBS)) {
 280                 return 0;
 281         }
 282
 283         can_write_reg(chip, DISABLE_INTERRUPTS, SJAIER); //disable interrupts for a moment
 284         sja1000p_read(chip, obj);
 285         can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER); //enable interrupts
 286         return 1;
 287 }
 288
 289 #define MAX_TRANSMIT_WAIT_LOOPS 10
 290 /**
 291  * sja1000p_pre_write_config: - prepares message object for message transmission
 292  * @chip: pointer to chip state structure
 293  * @obj: pointer to message object state structure
 294  * @msg: pointer to CAN message
 295  *
 296  * This function prepares selected message object for future initiation
 297  * of message transmission by sja1000p_send_msg() function.
 298  * The CAN message data and message ID are transfered from @msg slot
 299  * into chip buffer in this function.
 300  * Return Value: negative value reports error.
 301  * File: src/sja1000p.c
 302  */
 303 int sja1000p_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
 304                                                         struct canmsg_t *msg)
 305 {
 306         int i=0;
 307         unsigned int id;
 308         int status;
 309
 310         /* Wait until Transmit Buffer Status is released */
 311         while ( !((status=can_read_reg(chip, SJASR)) & SR_TBS) &&
 312                                                 i++<MAX_TRANSMIT_WAIT_LOOPS) {
 313                 udelay(i);
 314         }
 315
 316         if(status & SR_BS) {
 317                 /* Try to recover from error condition */
 318                 DEBUGMSG("sja1000p_pre_write_config bus-off recover 0x%x\n",status);
 319                 sja1000p_enable_configuration(chip);
 320                 can_write_reg(chip, 0, SJARXERR);
 321                 can_write_reg(chip, 0, SJATXERR1);
 322                 can_read_reg(chip, SJAECC);
 323                 sja1000p_disable_configuration(chip);
 324         }
 325         if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
 326                 CANMSG("Transmit timed out, cancelling\n");
 327 // here we should check if there is no write/select waiting for this
 328 // transmit. If so, set error ret and wake up.
 329 // CHECKME: if we do not disable IER_TIE (TX IRQ) here we get interrupt
 330 // immediately
 331                 can_write_reg(chip, CMR_AT, SJACMR);
 332                 i=0;
 333                 while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
 334                                                 i++<MAX_TRANSMIT_WAIT_LOOPS) {
 335                         udelay(i);
 336                 }
 337                 if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
 338                         CANMSG("Could not cancel, please reset\n");
 339                         return -EIO;
 340                 }
 341         }
 342         msg->length &= FRM_DLC_M;
 343         can_write_reg(chip, ((msg->flags&MSG_EXT)?FRM_FF:0) |
 344                 ((msg->flags & MSG_RTR) ? FRM_RTR : 0) |
 345                 msg->length, SJAFRM);
 346         if(msg->flags&MSG_EXT) {
 347                 id=msg->id<<3;
 348                 can_write_reg(chip, id & 0xff, SJAID3);
 349                 id >>= 8;
 350                 can_write_reg(chip, id & 0xff, SJAID2);
 351                 id >>= 8;
 352                 can_write_reg(chip, id & 0xff, SJAID1);
 353                 id >>= 8;
 354                 can_write_reg(chip, id, SJAID0);
 355                 for(i=0; i < msg->length; i++) {
 356                         can_write_reg(chip, msg->data[i], SJADATE+i);
 357                 }
 358         } else {
 359                 id=msg->id<<5;
 360                 can_write_reg(chip, (id >> 8) & 0xff, SJAID0);
 361                 can_write_reg(chip, id & 0xff, SJAID1);
 362                 for(i=0; i < msg->length; i++) {
 363                         can_write_reg(chip, msg->data[i], SJADATS+i);
 364                 }
 365         }
 366         return 0;
 367 }
 368
 369 /**
 370  * sja1000p_send_msg: - initiate message transmission
 371  * @chip: pointer to chip state structure
 372  * @obj: pointer to message object state structure
 373  * @msg: pointer to CAN message
 374  *
 375  * This function is called after sja1000p_pre_write_config() function,
 376  * which prepares data in chip buffer.
 377  * Return Value: negative value reports error.
 378  * File: src/sja1000p.c
 379  */
 380 int sja1000p_send_msg(struct chip_t *chip, struct msgobj_t *obj,
 381                                                         struct canmsg_t *msg)
 382 {
 383         can_write_reg(chip, CMR_TR, SJACMR);
 384
 385         return 0;
 386 }
 387
 388 /**
 389  * sja1000p_check_tx_stat: - checks state of transmission engine
 390  * @chip: pointer to chip state structure
 391  *
 392  * Return Value: negative value reports error.
 393  *      Positive return value indicates transmission under way status.
 394  *      Zero value indicates finishing of all issued transmission requests.
 395  * File: src/sja1000p.c
 396  */
 397 int sja1000p_check_tx_stat(struct chip_t *chip)
 398 {
 399         if (can_read_reg(chip,SJASR) & SR_TCS)
 400                 return 0;
 401         else
 402                 return 1;
 403 }
 404
 405 /**
 406  * sja1000p_set_btregs: -  configures bitrate registers
 407  * @chip: pointer to chip state structure
 408  * @btr0: bitrate register 0
 409  * @btr1: bitrate register 1
 410  *
 411  * Return Value: negative value reports error.
 412  * File: src/sja1000p.c
 413  */
 414 int sja1000p_set_btregs(struct chip_t *chip, unsigned short btr0,
 415                                                         unsigned short btr1)
 416 {
 417         if (sja1000p_enable_configuration(chip))
 418                 return -ENODEV;
 419
 420         can_write_reg(chip, btr0, SJABTR0);
 421         can_write_reg(chip, btr1, SJABTR1);
 422
 423         sja1000p_disable_configuration(chip);
 424
 425         return 0;
 426 }
 427
 428 /**
 429  * sja1000p_stop_chip: -  starts chip message processing
 430  * @chip: pointer to chip state structure
 431  *
 432  * Return Value: negative value reports error.
 433  * File: src/sja1000p.c
 434  */
 435 int sja1000p_start_chip(struct chip_t *chip)
 436 {
 437         enum sja1000_PeliCAN_MOD flags;
 438
 439         flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
 440         can_write_reg(chip, flags, SJAMOD);
 441
 442         return 0;
 443 }
 444
 445 /**
 446  * sja1000p_stop_chip: -  stops chip message processing
 447  * @chip: pointer to chip state structure
 448  *
 449  * Return Value: negative value reports error.
 450  * File: src/sja1000p.c
 451  */
 452 int sja1000p_stop_chip(struct chip_t *chip)
 453 {
 454         enum sja1000_PeliCAN_MOD flags;
 455
 456         flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
 457         can_write_reg(chip, flags|MOD_RM, SJAMOD);
 458
 459         return 0;
 460 }
 461
 462
 463 /**
 464  * sja1000p_remote_request: - configures message object and asks for RTR message
 465  * @chip: pointer to chip state structure
 466  * @obj: pointer to message object structure
 467  *
 468  * Return Value: negative value reports error.
 469  * File: src/sja1000p.c
 470  */
 471 int sja1000p_remote_request(struct chip_t *chip, struct msgobj_t *obj)
 472 {
 473         CANMSG("sja1000p_remote_request not implemented\n");
 474         return -ENOSYS;
 475 }
 476
 477 /**
 478  * sja1000p_standard_mask: - setup of mask for message filtering
 479  * @chip: pointer to chip state structure
 480  * @code: can message acceptance code
 481  * @mask: can message acceptance mask
 482  *
 483  * Return Value: negative value reports error.
 484  * File: src/sja1000p.c
 485  */
 486 int sja1000p_standard_mask(struct chip_t *chip, unsigned short code,
 487                 unsigned short mask)
 488 {
 489         CANMSG("sja1000p_standard_mask not implemented\n");
 490         return -ENOSYS;
 491 }
 492
 493 /**
 494  * sja1000p_clear_objects: - clears state of all message object residing in chip
 495  * @chip: pointer to chip state structure
 496  *
 497  * Return Value: negative value reports error.
 498  * File: src/sja1000p.c
 499  */
 500 int sja1000p_clear_objects(struct chip_t *chip)
 501 {
 502         CANMSG("sja1000p_clear_objects not implemented\n");
 503         return -ENOSYS;
 504 }
 505
 506 /**
 507  * sja1000p_config_irqs: - tunes chip hardware interrupt delivery
 508  * @chip: pointer to chip state structure
 509  * @irqs: requested chip IRQ configuration
 510  *
 511  * Return Value: negative value reports error.
 512  * File: src/sja1000p.c
 513  */
 514 int sja1000p_config_irqs(struct chip_t *chip, short irqs)
 515 {
 516         CANMSG("sja1000p_config_irqs not implemented\n");
 517         return -ENOSYS;
 518 }
 519
 520 /**
 521  * sja1000p_irq_write_handler: - part of ISR code responsible for transmit events
 522  * @chip: pointer to chip state structure
 523  * @obj: pointer to attached queue description
 524  *
 525  * The main purpose of this function is to read message from attached queues
 526  * and transfer message contents into CAN controller chip.
 527  * This subroutine is called by
 528  * sja1000p_irq_write_handler() for transmit events.
 529  * File: src/sja1000p.c
 530  */
 531 void sja1000p_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
 532 {
 533         int cmd;
 534
 535         if(obj->tx_slot){
 536                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 537                 obj->tx_slot=NULL;
 538         }
 539
 540         cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
 541         if(cmd<0)
 542                 return;
 543
 544         if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
 545                 obj->ret = -1;
 546                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
 547                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 548                 obj->tx_slot=NULL;
 549                 return;
 550         }
 551         if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
 552                 obj->ret = -1;
 553                 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
 554                 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 555                 obj->tx_slot=NULL;
 556                 return;
 557         }
 558
 559 }
 560
 561 #define MAX_RETR 10
 562
 563 /**
 564  * sja1000p_irq_handler: - interrupt service routine
 565  * @irq: interrupt vector number, this value is system specific
 566  * @dev_id: driver private pointer registered at time of request_irq() call.
 567  *      The CAN driver uses this pointer to store relationship of interrupt
 568  *      to chip state structure - @struct chip_t
 569  * @regs: system dependent value pointing to registers stored in exception frame
 570  *
 571  * Interrupt handler is activated when state of CAN controller chip changes,
 572  * there is message to be read or there is more space for new messages or
 573  * error occurs. The receive events results in reading of the message from
 574  * CAN controller chip and distribution of message through attached
 575  * message queues.
 576  * File: src/sja1000p.c
 577  */
 578 irqreturn_t sja1000p_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 579 {
 580         int irq_register, status, error_code;
 581         int static retransmitted=0; /* FIXME - should go into chip struct */
 582         struct chip_t *chip=(struct chip_t *)dev_id;
 583         struct msgobj_t *obj=chip->msgobj[0];
 584
 585         irq_register=can_read_reg(chip,SJAIR);
 586 //      DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
 587 //      DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
 588 //                                      can_read_reg(chip,SJASR));
 589
 590         if ((irq_register & (IR_BEI|IR_EPI|IR_DOI|IR_EI|IR_TI|IR_RI)) == 0)
 591                 return IRQ_NONE;
 592
 593         if(!obj->flags & OBJ_BUFFERS_ALLOCATED) {
 594                 CANMSG("sja1000p_irq_handler: called with device closed, irq_register 0x%02x\n", irq_register);
 595                 return IRQ_NONE;
 596         }
 597
 598         if ((irq_register & IR_RI) != 0) {
 599                 DEBUGMSG("sja1000_irq_handler: RI\n");
 600                 sja1000p_read(chip,obj);
 601                 obj->ret = 0;
 602         }
 603         if ((irq_register & IR_TI) != 0) {
 604                 DEBUGMSG("sja1000_irq_handler: TI\n");
 605                 obj->ret = 0;
 606                 set_bit(OBJ_TX_REQUEST,&obj->flags);
 607                 while(!test_and_set_bit(OBJ_TX_LOCK,&obj->flags)){
 608                         clear_bit(OBJ_TX_REQUEST,&obj->flags);
 609
 610                         if (can_read_reg(chip, SJASR) & SR_TBS)
 611                                 sja1000p_irq_write_handler(chip, obj);
 612
 613                         clear_bit(OBJ_TX_LOCK,&obj->flags);
 614                         if(!test_bit(OBJ_TX_REQUEST,&obj->flags)) break;
 615                         DEBUGMSG("TX looping in sja1000_irq_handler\n");
 616                 }
 617         }
 618         if ((irq_register & (IR_EI|IR_BEI|IR_EPI|IR_DOI)) != 0) {
 619                 // Some error happened
 620                 status=can_read_reg(chip,SJASR);
 621                 error_code=can_read_reg(chip,SJAECC);
 622                 CANMSG("Error: status register: 0x%x irq_register: 0x%02x error: 0x%02x\n",
 623                         status, irq_register, error_code);
 624 // FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
 625 // Reset flag set to 0 if chip is already off the bus. Full state report
 626                 obj->ret=-1;
 627
 628                 if(error_code == 0xd9) {
 629                         obj->ret= -ENXIO;
 630                         /* no such device or address - no ACK received */
 631                 }
 632                 if(retransmitted++>MAX_RETR) {
 633                         can_write_reg(chip, CMR_AT, SJACMR); // cancel any transmition
 634                         retransmitted = 0;
 635                 }
 636                 if(status&SR_BS) {
 637                         CANMSG("bus-off, resetting sja1000p\n");
 638                         can_write_reg(chip, 0, SJAMOD);
 639                 }
 640
 641                 if(obj->tx_slot){
 642                         canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_BUS);
 643                         /*canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
 644                         obj->tx_slot=NULL;*/
 645                 }
 646
 647         } else {
 648                 retransmitted=0;
 649         }
 650
 651         return IRQ_HANDLED;
 652 }
 653
 654 /**
 655  * sja1000p_wakeup_tx: - wakeups TX processing
 656  * @chip: pointer to chip state structure
 657  * @obj: pointer to message object structure
 658  *
 659  * Return Value: negative value reports error.
 660  * File: src/sja1000p.c
 661  */
 662 int sja1000p_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj)
 663 {
 664          /* dummy lock to prevent preemption fully portable way */
 665         spinlock_t dummy_lock;
 666
 667         /*  preempt_disable() */
 668         spin_lock_init(&dummy_lock);
 669         spin_lock(&dummy_lock);
 670
 671         set_bit(OBJ_TX_REQUEST,&obj->flags);
 672         while(!test_and_set_bit(OBJ_TX_LOCK,&obj->flags)){
 673                 clear_bit(OBJ_TX_REQUEST,&obj->flags);
 674
 675                 if (can_read_reg(chip, SJASR) & SR_TBS)
 676                         sja1000p_irq_write_handler(chip, obj);
 677
 678                 clear_bit(OBJ_TX_LOCK,&obj->flags);
 679                 if(!test_bit(OBJ_TX_REQUEST,&obj->flags)) break;
 680                 DEBUGMSG("TX looping in sja1000p_wakeup_tx\n");
 681         }
 682
 683         /* preempt_enable(); */
 684         spin_unlock(&dummy_lock);
 685         return 0;
 686 }
 687
 688 int sja1000p_register(struct chipspecops_t *chipspecops)
 689 {
 690         CANMSG("initializing sja1000p chip operations\n");
 691         chipspecops->chip_config=sja1000p_chip_config;
 692         chipspecops->baud_rate=sja1000p_baud_rate;
 693         chipspecops->standard_mask=sja1000p_standard_mask;
 694         chipspecops->extended_mask=sja1000p_extended_mask;
 695         chipspecops->message15_mask=sja1000p_extended_mask;
 696         chipspecops->clear_objects=sja1000p_clear_objects;
 697         chipspecops->config_irqs=sja1000p_config_irqs;
 698         chipspecops->pre_read_config=sja1000p_pre_read_config;
 699         chipspecops->pre_write_config=sja1000p_pre_write_config;
 700         chipspecops->send_msg=sja1000p_send_msg;
 701         chipspecops->check_tx_stat=sja1000p_check_tx_stat;
 702         chipspecops->wakeup_tx=sja1000p_wakeup_tx;
 703         chipspecops->remote_request=sja1000p_remote_request;
 704         chipspecops->enable_configuration=sja1000p_enable_configuration;
 705         chipspecops->disable_configuration=sja1000p_disable_configuration;
 706         chipspecops->set_btregs=sja1000p_set_btregs;
 707         chipspecops->start_chip=sja1000p_start_chip;
 708         chipspecops->stop_chip=sja1000p_stop_chip;
 709         chipspecops->irq_handler=sja1000p_irq_handler;
 710         return 0;
 711 }