2 * Header file for the Linux CAN-bus driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * This software is released under the GPL-License.
5 * Version 0.7 6 Aug 2001
8 int i82527_enable_configuration(struct chip_t *chip);
9 int i82527_disable_configuration(struct chip_t *chip);
10 int i82527_chip_config(struct chip_t *chip);
11 int i82527_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
12 int sampl_pt, int flags);
13 int i82527_standard_mask(struct chip_t *chip, unsigned short code,
15 int i82527_extended_mask(struct chip_t *chip, unsigned long code,
17 int i82527_message15_mask(struct chip_t *chip, unsigned long code,
19 int i82527_clear_objects(struct chip_t *chip);
20 int i82527_config_irqs(struct chip_t *chip, short irqs);
21 int i82527_pre_read_config(struct chip_t *chip, struct msgobj_t *obj);
22 int i82527_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
23 struct canmsg_t *msg);
24 int i82527_send_msg(struct chip_t *chip, struct msgobj_t *obj,
25 struct canmsg_t *msg);
26 int i82527_remote_request(struct chip_t *chip, struct msgobj_t *obj);
27 int i82527_set_btregs(struct chip_t *chip, unsigned short btr0,
29 int i82527_start_chip(struct chip_t *chip);
30 int i82527_stop_chip(struct chip_t *chip);
31 int i82527_check_tx_stat(struct chip_t *chip);
33 #define iCTL 0x00 // Control Register
34 #define iSTAT 0x01 // Status Register
35 #define iCPU 0x02 // CPU Interface Register
36 #define iHSR 0x04 // High Speed Read
37 #define iSGM0 0x06 // Standard Global Mask byte 0
39 #define iEGM0 0x08 // Extended Global Mask byte 0
43 #define i15M0 0x0c // Message 15 Mask byte 0
47 #define iCLK 0x1f // Clock Out Register
48 #define iBUS 0x2f // Bus Configuration Register
49 #define iBT0 0x3f // Bit Timing Register byte 0
51 #define iIRQ 0x5f // Interrupt Register
52 #define iP1C 0x9f // Port 1 Register
53 #define iP2C 0xaf // Port 2 Register
54 #define iP1I 0xbf // Port 1 Data In Register
55 #define iP2I 0xcf // Port 2 Data In Register
56 #define iP1O 0xdf // Port 1 Data Out Register
57 #define iP2O 0xef // Port 2 Data Out Register
58 #define iSRA 0xff // Serial Reset Address
60 #define iMSGCTL0 0x00 /* First Control register */
61 #define iMSGCTL1 0x01 /* Second Control register */
62 #define iMSGID0 0x02 /* First Byte of Message ID */
66 #define iMSGCFG 0x06 /* Message Configuration */
67 #define iMSGDAT0 0x07 /* First Data Byte */
76 /* Control Register (0x00) */
78 iCTL_INI = 1, // Initialization
79 iCTL_IE = 1<<1, // Interrupt Enable
80 iCTL_SIE = 1<<2, // Status Interrupt Enable
81 iCTL_EIE = 1<<3, // Error Interrupt Enable
82 iCTL_CCE = 1<<6 // Change Configuration Enable
85 /* Status Register (0x01) */
87 iSTAT_TXOK = 1<<3, // Transmit Message Successfully
88 iSTAT_RXOK = 1<<4, // Receive Message Successfully
89 iSTAT_WAKE = 1<<5, // Wake Up Status
90 iSTAT_WARN = 1<<6, // Warning Status
91 iSTAT_BOFF = 1<<7 // Bus Off Status
94 /* CPU Interface Register (0x02) */
96 iCPU_CEN = 1, // Clock Out Enable
97 iCPU_MUX = 1<<2, // Multiplex
98 iCPU_SLP = 1<<3, // Sleep
99 iCPU_PWD = 1<<4, // Power Down Mode
100 iCPU_DMC = 1<<5, // Divide Memory Clock
101 iCPU_DSC = 1<<6, // Divide System Clock
102 iCPU_RST = 1<<7 // Hardware Reset Status
105 /* Clock Out Register (0x1f) */
107 iCLK_CD0 = 1, // Clock Divider bit 0
111 iCLK_SL0 = 1<<4, // Slew Rate bit 0
115 /* Bus Configuration Register (0x2f) */
117 iBUS_DR0 = 1, // Disconnect RX0 Input
118 iBUS_DR1 = 1<<1, // Disconnect RX1 Input
119 iBUS_DT1 = 1<<3, // Disconnect TX1 Output
120 iBUS_POL = 1<<5, // Polarity
121 iBUS_CBY = 1<<6 // Comparator Bypass
124 #define RESET 1 // Bit Pair Reset Status
125 #define SET 2 // Bit Pair Set Status
126 #define UNCHANGED 3 // Bit Pair Unchanged
128 /* Message Control Register 0 (Base Address + 0x0) */
129 enum i82527_iMSGCTL0 {
130 INTPD_SET = SET, // Interrupt pending
131 INTPD_RES = RESET, // No Interrupt pending
132 INTPD_UNC = UNCHANGED,
133 RXIE_SET = SET<<2, // Receive Interrupt Enable
134 RXIE_RES = RESET<<2, // Receive Interrupt Disable
135 RXIE_UNC = UNCHANGED<<2,
136 TXIE_SET = SET<<4, // Transmit Interrupt Enable
137 TXIE_RES = RESET<<4, // Transmit Interrupt Disable
138 TXIE_UNC = UNCHANGED<<4,
139 MVAL_SET = SET<<6, // Message Valid
140 MVAL_RES = RESET<<6, // Message Invalid
141 MVAL_UNC = UNCHANGED<<6
144 /* Message Control Register 1 (Base Address + 0x01) */
145 enum i82527_iMSGCTL1 {
146 NEWD_SET = SET, // New Data
147 NEWD_RES = RESET, // No New Data
148 NEWD_UNC = UNCHANGED,
149 MLST_SET = SET<<2, // Message Lost
150 MLST_RES = RESET<<2, // No Message Lost
151 MLST_UNC = UNCHANGED<<2,
152 CPUU_SET = SET<<2, // CPU Updating
153 CPUU_RES = RESET<<2, // No CPU Updating
154 CPUU_UNC = UNCHANGED<<2,
155 TXRQ_SET = SET<<4, // Transmission Request
156 TXRQ_RES = RESET<<4, // No Transmission Request
157 TXRQ_UNC = UNCHANGED<<4,
158 RMPD_SET = SET<<6, // Remote Request Pending
159 RMPD_RES = RESET<<6, // No Remote Request Pending
160 RMPD_UNC = UNCHANGED<<6
163 /* Message Configuration Register (Base Address + 0x06) */
164 enum i82527_iMSGCFG {
165 MCFG_XTD = 1<<2, // Extended Identifier
166 MCFG_DIR = 1<<3 // Direction is Transmit