2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.2 9 Jul 2003
10 #include <linux/autoconf.h>
12 #include <linux/sched.h>
13 #include <linux/delay.h>
16 #include "../include/main.h"
17 #include "../include/sja1000.h"
19 void sja1000_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj);
20 void sja1000_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj);
22 int sja1000_enable_configuration(struct chip_t *chip)
27 disable_irq(chip->chip_irq);
29 flags=can_read_reg(chip,SJACR);
31 while ((!(flags & CR_RR)) && (i<=10)) {
32 can_write_reg(chip,flags|CR_RR,SJACR);
35 flags=can_read_reg(chip,SJACR);
38 CANMSG("Reset error\n");
39 enable_irq(chip->chip_irq);
46 int sja1000_disable_configuration(struct chip_t *chip)
51 flags=can_read_reg(chip,SJACR);
53 while ( (flags & CR_RR) && (i<=10) ) {
54 can_write_reg(chip,flags & (CR_RIE|CR_TIE|CR_EIE|CR_OIE),SJACR);
57 flags=can_read_reg(chip,SJACR);
60 CANMSG("Error leaving reset status\n");
64 enable_irq(chip->chip_irq);
69 int sja1000_chip_config(struct chip_t *chip)
71 if (sja1000_enable_configuration(chip))
74 /* Set mode, clock out, comparator */
75 can_write_reg(chip,chip->sja_cdr_reg,SJACDR);
76 /* Set driver output configuration */
77 can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
79 if (sja1000_standard_mask(chip,0x0000, 0xffff))
84 if (sja1000_baud_rate(chip,1000*baudrate,chip->clock,0,75,0))
87 /* Enable hardware interrupts */
88 can_write_reg(chip,(CR_RIE|CR_TIE|CR_EIE|CR_OIE),SJACR);
90 sja1000_disable_configuration(chip);
95 int sja1000_standard_mask(struct chip_t *chip, unsigned short code, unsigned short mask)
97 unsigned char write_code, write_mask;
99 if (sja1000_enable_configuration(chip))
102 /* The acceptance code bits (SJAACR bits 0-7) and the eight most
103 * significant bits of the message identifier (id.10 to id.3) must be
104 * equal to those bit positions which are marked relevant by the
105 * acceptance mask bits (SJAAMR bits 0-7).
106 * (id.10 to id.3) = (SJAACR.7 to SJAACR.0) v (SJAAMR.7 to SJAAMR.0)
107 * (Taken from Philips sja1000 Data Sheet)
109 write_code = (unsigned char) code >> 3;
110 write_mask = (unsigned char) mask >> 3;
112 can_write_reg(chip,write_code,SJAACR);
113 can_write_reg(chip,write_mask,SJAAMR);
115 DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
116 DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
118 sja1000_disable_configuration(chip);
123 /* Set communication parameters.
124 * param rate baud rate in Hz
125 * param clock frequency of sja1000 clock in Hz (ISA osc is 14318000)
126 * param sjw synchronization jump width (0-3) prescaled clock cycles
127 * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
128 * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
130 int sja1000_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
131 int sampl_pt, int flags)
133 int best_error = 1000000000, error;
134 int best_tseg=0, best_brp=0, best_rate=0, brp=0;
135 int tseg=0, tseg1=0, tseg2=0;
137 if (sja1000_enable_configuration(chip))
142 /* tseg even = round down, odd = round up */
143 for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
144 brp = clock/((1+tseg/2)*rate)+tseg%2;
145 if (brp == 0 || brp > 64)
147 error = rate - clock/(brp*(1+tseg/2));
150 if (error <= best_error) {
154 best_rate = clock/(brp*(1+tseg/2));
157 if (best_error && (rate/best_error < 10)) {
158 CANMSG("baud rate %d is not possible with %d Hz clock\n",
160 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
161 best_rate, best_brp, best_tseg, tseg1, tseg2);
164 tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
167 if (tseg2 > MAX_TSEG2)
169 tseg1 = best_tseg-tseg2-2;
170 if (tseg1 > MAX_TSEG1) {
172 tseg2 = best_tseg-tseg1-2;
175 DEBUGMSG("Setting %d bps.\n", best_rate);
176 DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
177 best_brp, best_tseg, tseg1, tseg2,
178 (100*(best_tseg-tseg2)/(best_tseg+1)));
181 can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
182 can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | tseg2<<4 | tseg1,
184 // can_write_reg(chip, OCR_MODE_NORMAL | OCR_TX0_LH | OCR_TX1_ZZ, SJAOCR);
185 /* BASIC mode, bypass input comparator */
186 // can_write_reg(chip, CDR_CBP| /* CDR_CLK_OFF | */ 7, SJACDR);
188 sja1000_disable_configuration(chip);
193 int sja1000_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
197 i=can_read_reg(chip,SJASR);
201 for (i=0; i<0x20; i++)
202 CANMSG("0x%x is 0x%x\n",i,can_read_reg(chip,i));
205 sja1000_start_chip(chip);
207 // disable interrupts for a moment
208 can_write_reg(chip, 0, SJACR);
210 sja1000_irq_read_handler(chip, obj);
213 can_write_reg(chip, CR_OIE | CR_EIE | CR_TIE | CR_RIE, SJACR);
219 #define MAX_TRANSMIT_WAIT_LOOPS 10
221 int sja1000_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
222 struct canmsg_t *msg)
226 sja1000_start_chip(chip); //sja1000 goes automatically into reset mode on errors
228 /* Wait until Transmit Buffer Status is released */
229 while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
230 i++<MAX_TRANSMIT_WAIT_LOOPS) {
234 if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
235 CANMSG("Transmit timed out, cancelling\n");
236 can_write_reg(chip, CMR_AT, SJACMR);
238 while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
239 i++<MAX_TRANSMIT_WAIT_LOOPS) {
242 if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
243 CANMSG("Could not cancel, please reset\n");
248 id = (msg->id<<5) | ((msg->flags&MSG_RTR)?ID0_RTR:0) | msg->length;
250 can_write_reg(chip, id>>8, SJATXID1);
251 can_write_reg(chip, id & 0xff , SJATXID0);
253 for (i=0; i<msg->length; i++)
254 can_write_reg(chip, msg->data[i], SJATXDAT0+i);
259 int sja1000_send_msg(struct chip_t *chip, struct msgobj_t *obj,
260 struct canmsg_t *msg)
262 can_write_reg(chip, CMR_TR, SJACMR);
267 int sja1000_check_tx_stat(struct chip_t *chip)
269 if (can_read_reg(chip,SJASR) & SR_TCS)
275 int sja1000_set_btregs(struct chip_t *chip, unsigned short btr0,
278 if (sja1000_enable_configuration(chip))
281 can_write_reg(chip, btr0, SJABTR0);
282 can_write_reg(chip, btr1, SJABTR1);
284 sja1000_disable_configuration(chip);
289 int sja1000_start_chip(struct chip_t *chip)
291 unsigned short flags = 0;
293 flags = can_read_reg(chip, SJACR) & (CR_RIE|CR_TIE|CR_EIE|CR_OIE);
294 can_write_reg(chip, flags, SJACR);
299 int sja1000_stop_chip(struct chip_t *chip)
301 unsigned short flags = 0;
303 flags = can_read_reg(chip, SJACR) & (CR_RIE|CR_TIE|CR_EIE|CR_OIE);
304 can_write_reg(chip, flags|CR_RR, SJACR);
309 int sja1000_remote_request(struct chip_t *chip, struct msgobj_t *obj)
311 CANMSG("sja1000_remote_request not implemented\n");
315 int sja1000_extended_mask(struct chip_t *chip, unsigned long code,
318 CANMSG("sja1000_extended_mask not implemented\n");
322 int sja1000_clear_objects(struct chip_t *chip)
324 CANMSG("sja1000_clear_objects not implemented\n");
328 int sja1000_config_irqs(struct chip_t *chip, short irqs)
330 CANMSG("sja1000_config_irqs not implemented\n");
335 irqreturn_t sja1000_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
337 unsigned irq_register;
338 struct chip_t *chip=(struct chip_t *)dev_id;
339 struct msgobj_t *obj=chip->msgobj[0];
341 irq_register=can_read_reg(chip, SJAIR);
342 // DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
343 // DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
344 // can_read_reg(chip, SJASR));
346 if ((irq_register & (IR_WUI|IR_DOI|IR_EI|IR_TI|IR_RI)) == 0)
349 if ((irq_register & IR_RI) != 0)
350 sja1000_irq_read_handler(chip, obj);
352 if ((irq_register & IR_TI) != 0) {
353 set_bit(OBJ_TX_REQUEST,&obj->flags);
354 while(!test_and_set_bit(OBJ_TX_LOCK,&obj->flags)){
355 clear_bit(OBJ_TX_REQUEST,&obj->flags);
357 if (can_read_reg(chip, SJASR) & SR_TBS)
358 sja1000_irq_write_handler(chip, obj);
360 clear_bit(OBJ_TX_LOCK,&obj->flags);
361 if(!test_bit(OBJ_TX_REQUEST,&obj->flags)) break;
365 if ((irq_register & (IR_EI|IR_DOI)) != 0) {
366 // Some error happened
367 // FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
368 // Reset flag set to 0 if chip is already off the bus. Full state report
369 CANMSG("Error: status register: 0x%x irq_register: 0x%02x\n",
370 can_read_reg(chip, SJASR), irq_register);
374 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_BUS);
375 /*canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
383 void sja1000_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj)
388 id = can_read_reg(chip, SJARXID0) | (can_read_reg(chip, SJARXID1)<<8);
389 obj->rx_msg.length = id & 0x0f;
390 obj->rx_msg.flags = id&ID0_RTR ? MSG_RTR : 0;
391 obj->rx_msg.timestamp = 0;
393 obj->rx_msg.id = id>>5;
395 for (i=0; i<obj->rx_msg.length; i++)
396 obj->rx_msg.data[i]=can_read_reg(chip, SJARXDAT0 + i);
398 can_write_reg(chip, CMR_RRB, SJACMR);
400 canque_filter_msg2edges(obj->qends, &obj->rx_msg);
401 } while(can_read_reg(chip, SJASR) & SR_RBS);
404 void sja1000_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
409 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
413 cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
417 if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
419 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
420 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
424 if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
426 canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
427 canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
434 * sja1000_wakeup_tx: - wakeups TX processing
435 * @chip: pointer to chip state structure
436 * @obj: pointer to message object structure
438 * Return Value: negative value reports error.
439 * File: src/sja1000.c
441 int sja1000_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj)
443 /* dummy lock to prevent preemption fully portable way */
444 spinlock_t dummy_lock;
446 /* preempt_disable() */
447 spin_lock_init(&dummy_lock);
448 spin_lock(&dummy_lock);
450 set_bit(OBJ_TX_REQUEST,&obj->flags);
451 while(!test_and_set_bit(OBJ_TX_LOCK,&obj->flags)){
452 clear_bit(OBJ_TX_REQUEST,&obj->flags);
454 if (can_read_reg(chip, SJASR) & SR_TBS)
455 sja1000_irq_write_handler(chip, obj);
457 clear_bit(OBJ_TX_LOCK,&obj->flags);
458 if(!test_bit(OBJ_TX_REQUEST,&obj->flags)) break;
461 /* preempt_enable(); */
462 spin_unlock(&dummy_lock);
466 int sja1000_register(struct chipspecops_t *chipspecops)
468 chipspecops->chip_config = sja1000_chip_config;
469 chipspecops->baud_rate = sja1000_baud_rate;
470 chipspecops->standard_mask = sja1000_standard_mask;
471 chipspecops->extended_mask = sja1000_extended_mask;
472 chipspecops->message15_mask = sja1000_extended_mask;
473 chipspecops->clear_objects = sja1000_clear_objects;
474 chipspecops->config_irqs = sja1000_config_irqs;
475 chipspecops->pre_read_config = sja1000_pre_read_config;
476 chipspecops->pre_write_config = sja1000_pre_write_config;
477 chipspecops->send_msg = sja1000_send_msg;
478 chipspecops->check_tx_stat = sja1000_check_tx_stat;
479 chipspecops->wakeup_tx=sja1000_wakeup_tx;
480 chipspecops->remote_request = sja1000_remote_request;
481 chipspecops->enable_configuration = sja1000_enable_configuration;
482 chipspecops->disable_configuration = sja1000_disable_configuration;
483 chipspecops->set_btregs = sja1000_set_btregs;
484 chipspecops->start_chip = sja1000_start_chip;
485 chipspecops->stop_chip = sja1000_stop_chip;
486 chipspecops->irq_handler = sja1000_irq_handler;