lincan/src/pccan.c

   1 /* pccan.c
   2  * Linux CAN-bus device driver.
   3  * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
   4  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
   5  * email:pisa@cmp.felk.cvut.cz
   6  * This software is released under the GPL-License.
   7  * Version lincan-0.2  9 Jul 2003
   8  */
   9
  10 #include <linux/autoconf.h>
  11
  12 #include <linux/ioport.h>
  13 #include <linux/delay.h>
  14 #include <asm/errno.h>
  15 #include <asm/io.h>
  16 #include <asm/irq.h>
  17
  18 #include "../include/main.h"
  19 #include "../include/pccan.h"
  20 #include "../include/i82527.h"
  21 #include "../include/sja1000.h"
  22
  23 int pccanf_request_io(struct candevice_t *candev)
  24 {
  25         if (!can_request_io_region(candev->io_addr+0x4000,0x20,DEVICE_NAME)) {
  26                 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr+0x4000);
  27                 return -ENODEV;
  28         }
  29         else if (!can_request_io_region(candev->io_addr+0x6000,0x04,DEVICE_NAME)) {
  30                 can_release_io_region(candev->io_addr+0x4000,0x20);
  31                 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr+0x6000);
  32                 return -ENODEV;
  33         }
  34         else {
  35                 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr+0x4000, candev->io_addr+0x4000+0x20-1);
  36                 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr+0x6000, candev->io_addr+0x6000+0x04-1);
  37         }
  38         return 0;
  39 }
  40
  41 int pccand_request_io(struct candevice_t *candev)
  42 {
  43         if (pccanf_request_io(candev))
  44                 return -ENODEV;
  45
  46         if (!can_request_io_region(candev->io_addr+0x5000,0x20,DEVICE_NAME)) {
  47                 pccanf_release_io(candev);
  48                 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr+0x5000);
  49                 return -ENODEV;
  50         }
  51         else {
  52                 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr+0x5000, candev->io_addr+0x5000+0x20-1);
  53         }
  54         return 0;
  55 }
  56
  57 int pccanq_request_io(struct candevice_t *candev)
  58 {
  59         unsigned long io_addr;
  60         int i;
  61
  62         if (pccand_request_io(candev))
  63                 return -ENODEV;
  64
  65         for(i=0, io_addr=candev->io_addr+0x2000; i<8; i++, io_addr+=0x400) {
  66                 if (!can_request_io_region(io_addr,0x40,DEVICE_NAME)) {
  67                         CANMSG("Unable to open port: 0x%lx\n",io_addr);
  68                         while(i--){
  69                                 io_addr-=0x400;
  70                                 can_release_io_region(io_addr,0x40);
  71                         }
  72                         pccand_release_io(candev);
  73                         return -ENODEV;
  74                 }
  75                 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr, io_addr+0x40-1);
  76         }
  77         return 0;
  78 }
  79
  80 int pccanf_release_io(struct candevice_t *candev)
  81 {
  82         can_release_io_region(candev->io_addr+0x4000,0x20);
  83         can_release_io_region(candev->io_addr+0x6000,0x04);
  84
  85         return 0;
  86 }
  87
  88 int pccand_release_io(struct candevice_t *candev)
  89 {
  90         pccanf_release_io(candev);
  91         can_release_io_region(candev->io_addr+0x5000,0x20);
  92
  93         return 0;
  94 }
  95
  96 int pccanq_release_io(struct candevice_t *candev)
  97 {
  98         unsigned long io_addr;
  99         int i;
 100
 101         pccand_release_io(candev);
 102
 103         for(i=0, io_addr=candev->io_addr+0x2000; i<8; i++, io_addr+=0x400) {
 104                 can_release_io_region(io_addr,0x40);
 105         }
 106
 107         return 0;
 108 }
 109
 110 int pccanf_reset(struct candevice_t *candev)
 111 {
 112         int i=0;
 113
 114         DEBUGMSG("Resetting pccanf/s hardware ...\n");
 115         while (i < 1000000) {
 116                 i++;
 117                 outb(0x00,candev->res_addr);
 118         }
 119         outb(0x01,candev->res_addr);
 120         outb(0x00,candev->chip[0]->chip_base_addr+SJACR);
 121
 122         /* Check hardware reset status */
 123         i=0;
 124         while ( (inb(candev->chip[0]->chip_base_addr+SJACR) & CR_RR)
 125                                                                  && (i<=15) ) {
 126                 udelay(20000);
 127                 i++;
 128         }
 129         if (i>=15) {
 130                 CANMSG("Reset status timeout!\n");
 131                 CANMSG("Please check your hardware.\n");
 132                 return -ENODEV;
 133         }
 134         else
 135                 DEBUGMSG("Chip[0] reset status ok.\n");
 136
 137         return 0;
 138 }
 139
 140 int pccand_reset(struct candevice_t *candev)
 141 {
 142         int i=0,chip_nr=0;
 143
 144         DEBUGMSG("Resetting pccan-d hardware ...\n");
 145         while (i < 1000000) {
 146                 i++;
 147                 outb(0x00,candev->res_addr);
 148         }
 149         outb(0x01,candev->res_addr);
 150         outb(0x00,candev->chip[0]->chip_base_addr+SJACR);
 151         outb(0x00,candev->chip[1]->chip_base_addr+SJACR);
 152
 153         /* Check hardware reset status */
 154         i=0;
 155         for (chip_nr=0; chip_nr<2; chip_nr++) {
 156                 i=0;
 157                 while ( (inb(candev->chip[chip_nr]->chip_base_addr +
 158                                                 SJACR) & CR_RR) && (i<=15) ) {
 159                         udelay(20000);
 160                         i++;
 161                 }
 162                 if (i>=15) {
 163                         CANMSG("Reset status timeout!\n");
 164                         CANMSG("Please check your hardware.\n");
 165                         return -ENODEV;
 166                 }
 167                 else
 168                         DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
 169         }
 170         return 0;
 171 }
 172
 173 int pccanq_reset(struct candevice_t *candev)
 174 {
 175         int i=0,chip_nr=0;
 176
 177         for (i=0; i<4; i++)
 178                 disable_irq(candev->chip[i]->chip_irq);
 179
 180         DEBUGMSG("Resetting pccan-q hardware ...\n");
 181         while (i < 100000) {
 182                 i++;
 183                 outb(0x00,candev->res_addr);
 184         }
 185         outb_p(0x01,candev->res_addr);
 186
 187         outb(0x00,candev->chip[2]->chip_base_addr+SJACR);
 188         outb(0x00,candev->chip[3]->chip_base_addr+SJACR);
 189
 190         /* Check hardware reset status */
 191         for (chip_nr=0; chip_nr<2; chip_nr++) {
 192                 i=0;
 193                 while( (inb(candev->chip[chip_nr]->chip_base_addr +
 194                                                 iCPU) & iCPU_RST) && (i<=15) ) {
 195                         udelay(20000);
 196                         i++;
 197                 }
 198                 if (i>=15) {
 199                         CANMSG("Reset status timeout!\n");
 200                         CANMSG("Please check your hardware.\n");
 201                         return -ENODEV;
 202                 }
 203                 else
 204                         DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
 205         }
 206         for (chip_nr=2; chip_nr<4; chip_nr++) {
 207                 i=0;
 208                 while( (inb(candev->chip[chip_nr]->chip_base_addr +
 209                                                 SJACR) & CR_RR) && (i<=15) ) {
 210                         udelay(20000);
 211                         i++;
 212                 }
 213                 if (i>=15) {
 214                         CANMSG("Reset status timeout!\n");
 215                         CANMSG("Please check your hardware.\n");
 216                         return -ENODEV;
 217                 }
 218                 else
 219                         DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
 220         }
 221
 222         for (i=0; i<4; i++)
 223                 enable_irq(candev->chip[i]->chip_irq);
 224
 225         return 0;
 226 }
 227
 228 int pccan_init_hw_data(struct candevice_t *candev)
 229 {
 230         candev->res_addr=candev->io_addr+0x6001;
 231         candev->flags |= PROGRAMMABLE_IRQ;
 232
 233         if (!strcmp(candev->hwname,"pccan-q")) {
 234                 candev->nr_82527_chips=2;
 235                 candev->nr_sja1000_chips=2;
 236                 candev->nr_all_chips=4;
 237         }
 238         if (!strcmp(candev->hwname,"pccan-f") |
 239             !strcmp(candev->hwname,"pccan-s")) {
 240                 candev->nr_82527_chips=0;
 241                 candev->nr_sja1000_chips=1;
 242                 candev->nr_all_chips=1;
 243         }
 244         if (!strcmp(candev->hwname,"pccan-d")) {
 245                 candev->nr_82527_chips=0;
 246                 candev->nr_sja1000_chips=2;
 247                 candev->nr_all_chips=2;
 248         }
 249
 250         return 0;
 251 }
 252
 253 int pccan_init_chip_data(struct candevice_t *candev, int chipnr)
 254 {
 255         if (!strcmp(candev->hwname,"pccan-q")) {
 256                 if (chipnr<2) {
 257                         candev->chip[chipnr]->chip_type="i82527";
 258                         candev->chip[chipnr]->flags = CHIP_SEGMENTED;
 259                         candev->chip[chipnr]->int_cpu_reg=iCPU_DSC;
 260                         candev->chip[chipnr]->int_clk_reg=iCLK_SL1;
 261                         candev->chip[chipnr]->int_bus_reg=iBUS_CBY;
 262                         candev->chip[chipnr]->sja_cdr_reg = 0;
 263                         candev->chip[chipnr]->sja_ocr_reg = 0;
 264                 }
 265                 else{
 266                         candev->chip[chipnr]->chip_type="sja1000";
 267                         candev->chip[chipnr]->flags = 0;
 268                         candev->chip[chipnr]->int_cpu_reg = 0;
 269                         candev->chip[chipnr]->int_clk_reg = 0;
 270                         candev->chip[chipnr]->int_bus_reg = 0;
 271                         candev->chip[chipnr]->sja_cdr_reg =
 272                                                                 CDR_CLK_OFF;
 273                         candev->chip[chipnr]->sja_ocr_reg =
 274                                                 OCR_MODE_NORMAL | OCR_TX0_LH;
 275                 }
 276                 candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x2000+candev->io_addr;
 277         }
 278         else {
 279                 candev->chip[chipnr]->chip_type="sja1000";
 280                 candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x4000+candev->io_addr;
 281                 candev->chip[chipnr]->flags = 0;
 282                 candev->chip[chipnr]->int_cpu_reg = 0;
 283                 candev->chip[chipnr]->int_clk_reg = 0;
 284                 candev->chip[chipnr]->int_bus_reg = 0;
 285                 candev->chip[chipnr]->sja_cdr_reg = CDR_CLK_OFF;
 286                 candev->chip[chipnr]->sja_ocr_reg =
 287                                                 OCR_MODE_NORMAL | OCR_TX0_LH;
 288         }
 289
 290         candev->chip[chipnr]->clock = 16000000;
 291
 292         return 0;
 293 }
 294
 295 int pccan_init_obj_data(struct chip_t *chip, int objnr)
 296 {
 297         if (!strcmp(chip->chip_type,"sja1000")) {
 298                 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
 299                 chip->msgobj[objnr]->flags=0;
 300         }
 301         else {  /* The spacing for this card is 0x3c0 */
 302                 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr+(objnr+1)*0x10+(int)((objnr+1)/4)*0x3c0;
 303                 chip->msgobj[objnr]->flags=0;
 304         }
 305
 306         return 0;
 307 }
 308
 309 int pccan_program_irq(struct candevice_t *candev)
 310 {
 311         #define IRQ9 0x01
 312         #define IRQ3 0x02
 313         #define IRQ5 0x03
 314
 315         unsigned char irq_reg_value=0;
 316         int i;
 317
 318         for (i=0; i<4; i++) {
 319                 switch (candev->chip[i]->chip_irq) {
 320                         case 0: {
 321                                 break;
 322                         }
 323                         case 3: {
 324                                 irq_reg_value |= (IRQ3<<(i*2));
 325                                 break;
 326                         }
 327                         case 5: {
 328                                 irq_reg_value |= (IRQ5<<(i*2));
 329                                 break;
 330                         }
 331                         case 9: {
 332                                 irq_reg_value |= (IRQ9<<(i*2));
 333                                 break;
 334                         }
 335                         default: {
 336                                 CANMSG("Supplied interrupt is not supported by the hardware\n");
 337                                 return -ENODEV;
 338                         }
 339                 }
 340         }
 341         outb(irq_reg_value,0x6000+candev->io_addr);
 342         DEBUGMSG("Configured pccan hardware interrupts\n");
 343         outb(0x80,0x6000+candev->io_addr+0x02);
 344         DEBUGMSG("Selected pccan on-board 16 MHz oscillator\n");
 345
 346         return 0;
 347 }
 348
 349 inline void pccan_write_register(unsigned char data, unsigned long address)
 350 {
 351         outb(data,address);
 352 }
 353
 354 unsigned pccan_read_register(unsigned long address)
 355 {
 356         return inb(address);
 357 }
 358
 359 int pccanf_register(struct hwspecops_t *hwspecops)
 360 {
 361         hwspecops->request_io = pccanf_request_io;
 362         hwspecops->release_io = pccanf_release_io;
 363         hwspecops->reset = pccanf_reset;
 364         hwspecops->init_hw_data = pccan_init_hw_data;
 365         hwspecops->init_chip_data = pccan_init_chip_data;
 366         hwspecops->init_obj_data = pccan_init_obj_data;
 367         hwspecops->write_register = pccan_write_register;
 368         hwspecops->read_register = pccan_read_register;
 369         hwspecops->program_irq = pccan_program_irq;
 370         return 0;
 371 }
 372
 373
 374 int pccand_register(struct hwspecops_t *hwspecops)
 375 {
 376         hwspecops->request_io = pccand_request_io;
 377         hwspecops->release_io = pccand_release_io;
 378         hwspecops->reset = pccand_reset;
 379         hwspecops->init_hw_data = pccan_init_hw_data;
 380         hwspecops->init_chip_data = pccan_init_chip_data;
 381         hwspecops->init_obj_data = pccan_init_obj_data;
 382         hwspecops->write_register = pccan_write_register;
 383         hwspecops->read_register = pccan_read_register;
 384         hwspecops->program_irq = pccan_program_irq;
 385         return 0;
 386 }
 387
 388
 389 int pccanq_register(struct hwspecops_t *hwspecops)
 390 {
 391         hwspecops->request_io = pccanq_request_io;
 392         hwspecops->release_io = pccanq_release_io;
 393         hwspecops->reset = pccanq_reset;
 394         hwspecops->init_hw_data = pccan_init_hw_data;
 395         hwspecops->init_chip_data = pccan_init_chip_data;
 396         hwspecops->init_obj_data = pccan_init_obj_data;
 397         hwspecops->write_register = pccan_write_register;
 398         hwspecops->read_register = pccan_read_register;
 399         hwspecops->program_irq = pccan_program_irq;
 400         return 0;
 401 }