arm: Complete paging invalidations

arm: Complete paging invalidations

This patch is based on the original version by Jean-Philippe Brucker. It
fills different paging stubs:
- the arch_flush_cell_vcpu_caches stub, which is used by the core via
  config_commit each time the memory is remapped. It allows to
  invalidate the TLBs on all affected CPUs of the cell.
- the arch_paging_flush_cpu_caches function is used to flush the
  hypervisor page table entries when using the PAGE_MAP_COHERENT flag
  (useful for IOMMU, not currently in use on the arm side.)
- the arch_paging_flush_page_tlbs function is used to invalidate a TLB
  entry after modifying the hypervisor paging structures. It must ignore
  accesses done from the initial setup code at EL1, which are committed
  once at EL2 with a TLBIALLH, just before enabling the MMU.

arch_config_commit has nothing to do so far. Will change when an IOMMU is
supported.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>