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(parent: d18f67d) | patch
x86: Add AMD-V cell initialization/exit code
authorValentine Sinitsyn <valentine.sinitsyn@gmail.com>
Tue, 27 May 2014 18:21:30 +0000 (00:21 +0600)
committerJan Kiszka <jan.kiszka@siemens.com>
Sat, 1 Nov 2014 19:10:08 +0000 (20:10 +0100)
commitb7b802d4fc7b53d98e88e8394fcc5a53cfce8621
tree6a3fd93a6de4c55107c6c50f7e4984d99093524dtree | snapshot
parentd18f67dfe8bba42a8cbd05dc0beefae3f232c1a0commit | diff
x86: Add AMD-V cell initialization/exit code

AMD-V vendor-specific parts of vcpu_cell_init() and vcpu_cell_exit() are
implemented.

On startup, if AVIC is not available (which is usually the case) APIC is
mapped to cells read-only so only register writes are trapped and emulated.

On cell exits, the mapping is destroyed.

Signed-off-by: Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
hypervisor/arch/x86/svm.c diff | blob | history