2 * Jailhouse, a Linux-based partitioning hypervisor
4 * Copyright (c) Siemens AG, 2014
7 * Jan Kiszka <jan.kiszka@siemens.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
13 * Append "-device e1000,addr=19,netdev=..." to the QEMU command line for
14 * testing in the virtual machine. Adjust configs/e1000-demo.c for real
20 #ifdef CONFIG_UART_OXPCIE952
21 #define UART_BASE 0xe000
23 #define UART_BASE 0x2f8
26 #define E1000_REG_CTRL 0x0000
27 # define E1000_CTRL_LRST (1 << 3)
28 # define E1000_CTRL_ASDE (1 << 5)
29 # define E1000_CTRL_SLU (1 << 6)
30 # define E1000_CTRL_FRCSPD (1 << 12)
31 # define E1000_CTRL_RST (1 << 26)
32 #define E1000_REG_STATUS 0x0008
33 # define E1000_STATUS_LU (1 << 1)
34 # define E1000_STATUS_SPEEDSHFT 6
35 # define E1000_STATUS_SPEED (3 << E1000_STATUS_SPEEDSHFT)
36 #define E1000_REG_EERD 0x0014
37 # define E1000_EERD_START (1 << 0)
38 # define E1000_EERD_DONE (1 << 4)
39 # define E1000_EERD_ADDR_SHIFT 8
40 # define E1000_EERD_DATA_SHIFT 16
41 #define E1000_REG_MDIC 0x0020
42 # define E1000_MDIC_REGADD_SHFT 16
43 # define E1000_MDIC_PHYADD_SHFT 21
44 # define E1000_MDIC_OP_WRITE (0x1 << 26)
45 # define E1000_MDIC_OP_READ (0x2 << 26)
46 # define E1000_MDIC_READY (0x1 << 28)
47 #define E1000_REG_RCTL 0x0100
48 # define E1000_RCTL_EN (1 << 1)
49 # define E1000_RCTL_BAM (1 << 15)
50 # define E1000_RCTL_BSIZE_2048 (0 << 16)
51 # define E1000_RCTL_SECRC (1 << 26)
52 #define E1000_REG_TCTL 0x0400
53 # define E1000_TCTL_EN (1 << 1)
54 # define E1000_TCTL_PSP (1 << 3)
55 # define E1000_TCTL_CT_DEF (0xf << 4)
56 # define E1000_TCTL_COLD_DEF (0x40 << 12)
57 #define E1000_REG_TIPG 0x0410
58 # define E1000_TIPG_IPGT_DEF (10 << 0)
59 # define E1000_TIPG_IPGR1_DEF (10 << 10)
60 # define E1000_TIPG_IPGR2_DEF (10 << 20)
61 #define E1000_REG_RDBAL 0x2800
62 #define E1000_REG_RDBAH 0x2804
63 #define E1000_REG_RDLEN 0x2808
64 #define E1000_REG_RDH 0x2810
65 #define E1000_REG_RDT 0x2818
66 #define E1000_REG_TDBAL 0x3800
67 #define E1000_REG_TDBAH 0x3804
68 #define E1000_REG_TDLEN 0x3808
69 #define E1000_REG_TDH 0x3810
70 #define E1000_REG_TDT 0x3818
71 #define E1000_REG_RAL 0x5400
72 #define E1000_REG_RAH 0x5404
73 # define E1000_RAH_AV (1 << 31)
75 #define E1000_MAX_PHYADD 7
77 #define E1000_PHY_CTRL 0
78 # define E1000_PHYC_POWER_DOWN (1 << 11)
79 #define E1000_PHY_PSTATUS 1
80 #define E1000_PHY_ID1 2
87 } __attribute__((packed));
89 #define FRAME_TYPE_ANNOUNCE 0x004a
90 #define FRAME_TYPE_TARGET_ROLE 0x014a
91 #define FRAME_TYPE_PING 0x024a
92 #define FRAME_TYPE_PONG 0x034a
108 } __attribute__((packed));
129 } __attribute__((packed));
131 #define RX_DESCRIPTORS 8
132 #define RX_BUFFER_SIZE 2048
133 #define TX_DESCRIPTORS 8
135 static const char *speed_info[] = { "10", "100", "1000", "1000" };
137 static void *mmiobar;
138 static u8 buffer[RX_DESCRIPTORS * RX_BUFFER_SIZE];
139 static struct e1000_rxd rx_ring[RX_DESCRIPTORS];
140 static struct e1000_txd tx_ring[TX_DESCRIPTORS];
141 static unsigned int rx_idx, tx_idx;
142 static struct eth_header tx_packet;
143 static unsigned int phyadd;
145 static u16 phy_read(unsigned int reg)
149 mmio_write32(mmiobar + E1000_REG_MDIC,
150 (reg << E1000_MDIC_REGADD_SHFT) |
151 (phyadd << E1000_MDIC_PHYADD_SHFT) | E1000_MDIC_OP_READ);
153 val = mmio_read32(mmiobar + E1000_REG_MDIC);
155 } while (!(val & E1000_MDIC_READY));
160 static void phy_write(unsigned int reg, u16 val)
162 mmio_write32(mmiobar + E1000_REG_MDIC,
163 val | (reg << E1000_MDIC_REGADD_SHFT) |
164 (phyadd << E1000_MDIC_PHYADD_SHFT) | E1000_MDIC_OP_WRITE);
165 while (!(mmio_read32(mmiobar + E1000_REG_MDIC) & E1000_MDIC_READY))
169 static void send_packet(void *buffer, unsigned int size)
171 unsigned int idx = tx_idx;
173 memset(&tx_ring[idx], 0, sizeof(struct e1000_txd));
174 tx_ring[idx].addr = (unsigned long)buffer;
175 tx_ring[idx].len = size;
177 tx_ring[idx].ifcs = 1;
178 tx_ring[idx].eop = 1;
180 tx_idx = (tx_idx + 1) % TX_DESCRIPTORS;
181 mmio_write32(mmiobar + E1000_REG_TDT, tx_idx);
183 while (!tx_ring[idx].dd)
187 static struct eth_header *packet_received(void)
189 if (rx_ring[rx_idx].dd)
190 return (struct eth_header *)rx_ring[rx_idx].addr;
196 static void packet_reception_done(void)
198 unsigned int idx = rx_idx;
201 rx_idx = (rx_idx + 1) % RX_DESCRIPTORS;
202 mmio_write32(mmiobar + E1000_REG_RDT, idx);
205 void inmate_main(void)
207 enum { ROLE_UNDEFINED, ROLE_CONTROLLER, ROLE_TARGET } role;
208 unsigned long min = -1, max = 0, rtt;
209 struct eth_header *rx_packet;
210 unsigned long long start;
211 bool first_round = true;
218 printk_uart_base = UART_BASE;
220 bdf = pci_find_device(PCI_ID_ANY, PCI_ID_ANY, 0);
222 printk("No device found!\n");
225 printk("Found %04x:%04x at %02x:%02x.%x\n",
226 pci_read_config(bdf, PCI_CFG_VENDOR_ID, 2),
227 pci_read_config(bdf, PCI_CFG_DEVICE_ID, 2),
228 bdf >> 8, (bdf >> 3) & 0x1f, bdf & 0x3);
230 bar = pci_read_config(bdf, PCI_CFG_BAR, 4);
231 if ((bar & 0x6) == 0x4)
232 bar |= (u64)pci_read_config(bdf, PCI_CFG_BAR + 4, 4) << 32;
233 mmiobar = (void *)(bar & ~0xfUL);
234 map_range(mmiobar, 128 * 1024, MAP_UNCACHED);
235 printk("MMIO register BAR at %p\n", mmiobar);
237 pci_write_config(bdf, PCI_CFG_COMMAND,
238 PCI_CMD_MEM | PCI_CMD_MASTER, 2);
240 mmio_write32(mmiobar + E1000_REG_CTRL, E1000_CTRL_RST);
243 val = mmio_read32(mmiobar + E1000_REG_CTRL);
244 val &= ~(E1000_CTRL_LRST | E1000_CTRL_FRCSPD);
245 val |= E1000_CTRL_ASDE | E1000_CTRL_SLU;
246 mmio_write32(mmiobar + E1000_REG_CTRL, val);
248 for (phyadd = 0; phyadd <= E1000_MAX_PHYADD; phyadd++)
249 if (phy_read(E1000_PHY_ID1) != 0)
251 printk("PHY address: %d\n", phyadd);
252 /* power up again in case the previous user turned it off */
253 phy_write(E1000_PHY_CTRL,
254 phy_read(E1000_PHY_CTRL) & ~E1000_PHYC_POWER_DOWN);
256 printk("Waiting for link...");
257 while (!(mmio_read32(mmiobar + E1000_REG_STATUS) & E1000_STATUS_LU))
261 val = mmio_read32(mmiobar + E1000_REG_STATUS) & E1000_STATUS_SPEED;
262 val >>= E1000_STATUS_SPEEDSHFT;
263 printk("Link speed: %s Mb/s\n", speed_info[val]);
265 if (mmio_read32(mmiobar + E1000_REG_RAH) & E1000_RAH_AV) {
266 *(u32 *)mac = mmio_read32(mmiobar + E1000_REG_RAL);
267 *(u16 *)&mac[4] = mmio_read32(mmiobar + E1000_REG_RAH);
269 for (n = 0; n < 3; n++) {
270 mmio_write32(mmiobar + E1000_REG_EERD,
272 (n << E1000_EERD_ADDR_SHIFT));
274 eerd = mmio_read32(mmiobar + E1000_REG_EERD);
276 } while (!(eerd & E1000_EERD_DONE));
277 mac[n * 2] = (u8)(eerd >> E1000_EERD_DATA_SHIFT);
279 (u8)(eerd >> (E1000_EERD_DATA_SHIFT + 8));
283 printk("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
284 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
286 mmio_write32(mmiobar + E1000_REG_RAL, *(u32 *)mac);
287 mmio_write32(mmiobar + E1000_REG_RAH, *(u16 *)&mac[4] | E1000_RAH_AV);
289 for (n = 0; n < RX_DESCRIPTORS; n++)
290 rx_ring[n].addr = (unsigned long)&buffer[n * RX_BUFFER_SIZE];
291 mmio_write32(mmiobar + E1000_REG_RDBAL, (unsigned long)&rx_ring);
292 mmio_write32(mmiobar + E1000_REG_RDBAH, 0);
293 mmio_write32(mmiobar + E1000_REG_RDLEN, sizeof(rx_ring));
294 mmio_write32(mmiobar + E1000_REG_RDH, 0);
295 mmio_write32(mmiobar + E1000_REG_RDT, RX_DESCRIPTORS - 1);
297 val = mmio_read32(mmiobar + E1000_REG_RCTL);
298 val |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_BSIZE_2048 |
300 mmio_write32(mmiobar + E1000_REG_RCTL, val);
302 mmio_write32(mmiobar + E1000_REG_TDBAL, (unsigned long)&tx_ring);
303 mmio_write32(mmiobar + E1000_REG_TDBAH, 0);
304 mmio_write32(mmiobar + E1000_REG_TDLEN, sizeof(tx_ring));
305 mmio_write32(mmiobar + E1000_REG_TDH, 0);
306 mmio_write32(mmiobar + E1000_REG_TDT, 0);
308 val = mmio_read32(mmiobar + E1000_REG_TCTL);
309 val |= E1000_TCTL_EN | E1000_TCTL_PSP | E1000_TCTL_CT_DEF |
311 mmio_write32(mmiobar + E1000_REG_TCTL, val);
312 mmio_write32(mmiobar + E1000_REG_TIPG,
313 E1000_TIPG_IPGT_DEF | E1000_TIPG_IPGR1_DEF |
314 E1000_TIPG_IPGR2_DEF);
316 role = ROLE_UNDEFINED;
318 memcpy(tx_packet.src, mac, sizeof(tx_packet.src));
319 memset(tx_packet.dst, 0xff, sizeof(tx_packet.dst));
320 tx_packet.type = FRAME_TYPE_ANNOUNCE;
321 send_packet(&tx_packet, sizeof(tx_packet));
323 start = pm_timer_read();
324 while (pm_timer_read() - start < NS_PER_MSEC &&
325 role == ROLE_UNDEFINED) {
326 rx_packet = packet_received();
330 if (rx_packet->type == FRAME_TYPE_TARGET_ROLE) {
332 memcpy(tx_packet.dst, rx_packet->src,
333 sizeof(tx_packet.dst));
335 packet_reception_done();
338 if (role == ROLE_UNDEFINED) {
339 role = ROLE_CONTROLLER;
340 printk("Waiting for peer\n");
342 rx_packet = packet_received();
346 if (rx_packet->type == FRAME_TYPE_ANNOUNCE) {
347 memcpy(tx_packet.dst, rx_packet->src,
348 sizeof(tx_packet.dst));
349 packet_reception_done();
351 tx_packet.type = FRAME_TYPE_TARGET_ROLE;
352 send_packet(&tx_packet, sizeof(tx_packet));
355 packet_reception_done();
360 mmio_write32(mmiobar + E1000_REG_RCTL,
361 mmio_read32(mmiobar + E1000_REG_RCTL) & ~E1000_RCTL_BAM);
363 if (role == ROLE_CONTROLLER) {
364 printk("Running as controller\n");
365 tx_packet.type = FRAME_TYPE_PING;
367 start = pm_timer_read();
368 send_packet(&tx_packet, sizeof(tx_packet));
371 rx_packet = packet_received();
373 rx_packet->type != FRAME_TYPE_PONG);
374 packet_reception_done();
377 rtt = pm_timer_read() - start;
382 printk("Received pong, RTT: %6ld ns, "
383 "min: %6ld ns, max: %6ld ns\n",
390 printk("Running as target\n");
391 tx_packet.type = FRAME_TYPE_PONG;
393 rx_packet = packet_received();
394 if (!rx_packet || rx_packet->type != FRAME_TYPE_PING)
396 packet_reception_done();
397 send_packet(&tx_packet, sizeof(tx_packet));