From: Martin Jerabek Date: Wed, 11 May 2016 12:08:14 +0000 (+0200) Subject: sja1000 core, linux drivers X-Git-Url: http://rtime.felk.cvut.cz/gitweb/fpga/zynq/canbench-sw.git/commitdiff_plain/bfff60814ca72142b34f67fd4e44722245fce39b sja1000 core, linux drivers --- diff --git a/petalinux/subsystems/linux/configs/device-tree/pl.dtsi b/petalinux/subsystems/linux/configs/device-tree/pl.dtsi index e69de29..6b72fb7 100644 --- a/petalinux/subsystems/linux/configs/device-tree/pl.dtsi +++ b/petalinux/subsystems/linux/configs/device-tree/pl.dtsi @@ -0,0 +1,21 @@ +/* + * CAUTION: This file is automatically generated by Xilinx. + * Version: HSI 2015.4 + * Today is: Wed May 11 12:26:12 2016 +*/ + + +/ { + amba_pl: amba_pl { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges ; + sja1000_0: sja1000@43c00000 { + compatible = "xlnx,sja1000-1.0"; + reg = <0x43c00000 0x10000>; + xlnx,s00-axi-addr-width = <0x8>; + xlnx,s00-axi-data-width = <0x20>; + }; + }; +}; diff --git a/petalinux/subsystems/linux/configs/device-tree/system-top.dts b/petalinux/subsystems/linux/configs/device-tree/system-top.dts index 12360b5..b8ee1ca 100644 --- a/petalinux/subsystems/linux/configs/device-tree/system-top.dts +++ b/petalinux/subsystems/linux/configs/device-tree/system-top.dts @@ -3,3 +3,10 @@ / { }; +&sja1000_0 { + compatible = "nxp,sja1000"; + nxp,external-clock-frequency = <100000000>; + interrupt-parent = <&intc>; + interrupts = <0 61 4>; + reg-io-width = <4>; +}; diff --git a/petalinux/subsystems/linux/configs/kernel/config b/petalinux/subsystems/linux/configs/kernel/config index d8d9a6a..d853ee6 100644 --- a/petalinux/subsystems/linux/configs/kernel/config +++ b/petalinux/subsystems/linux/configs/kernel/config @@ -737,7 +737,13 @@ CONFIG_CAN_CALC_BITTIMING=y # CONFIG_CAN_GRCAN is not set # CONFIG_CAN_RCAR is not set # CONFIG_CAN_XILINXCAN is not set -# CONFIG_CAN_SJA1000 is not set +CONFIG_CAN_SJA1000=m +# CONFIG_CAN_SJA1000_ISA is not set +CONFIG_CAN_SJA1000_PLATFORM=m +# CONFIG_CAN_EMS_PCI is not set +# CONFIG_CAN_PEAK_PCI is not set +# CONFIG_CAN_KVASER_PCI is not set +# CONFIG_CAN_PLX_PCI is not set # CONFIG_CAN_C_CAN is not set # CONFIG_CAN_M_CAN is not set # CONFIG_CAN_CC770 is not set diff --git a/system/ip/sja1000_1.0/component.xml b/system/ip/sja1000_1.0/component.xml index 81980cb..f2c06f4 100644 --- a/system/ip/sja1000_1.0/component.xml +++ b/system/ip/sja1000_1.0/component.xml @@ -169,7 +169,7 @@ WIZ_DATA_WIDTH - 32 + 32 WIZ_NUM_REG @@ -181,252 +181,6 @@ - - IRQ - - - - - - - INTERRUPT - - - irq - - - - - - SENSITIVITY - LEVEL_HIGH - - - - - S_AXI_INTR - - - - - - - - - AWADDR - - - s_axi_intr_awaddr - - - - - AWPROT - - - s_axi_intr_awprot - - - - - AWVALID - - - s_axi_intr_awvalid - - - - - AWREADY - - - s_axi_intr_awready - - - - - WDATA - - - s_axi_intr_wdata - - - - - WSTRB - - - s_axi_intr_wstrb - - - - - WVALID - - - s_axi_intr_wvalid - - - - - WREADY - - - s_axi_intr_wready - - - - - BRESP - - - s_axi_intr_bresp - - - - - BVALID - - - s_axi_intr_bvalid - - - - - BREADY - - - s_axi_intr_bready - - - - - ARADDR - - - s_axi_intr_araddr - - - - - ARPROT - - - s_axi_intr_arprot - - - - - ARVALID - - - s_axi_intr_arvalid - - - - - ARREADY - - - s_axi_intr_arready - - - - - RDATA - - - s_axi_intr_rdata - - - - - RRESP - - - s_axi_intr_rresp - - - - - RVALID - - - s_axi_intr_rvalid - - - - - RREADY - - - s_axi_intr_rready - - - - - - WIZ_DATA_WIDTH - 32 - - - WIZ_NUM_REG - 5 - - - SUPPORTS_NARROW_BURST - 0 - - - - - S_AXI_INTR_RST - - - - - - - RST - - - s_axi_intr_aresetn - - - - - - POLARITY - ACTIVE_LOW - - - - - S_AXI_INTR_CLK - - - - - - - CLK - - - s_axi_intr_aclk - - - - - - ASSOCIATED_BUSIF - S_AXI_INTR - - - ASSOCIATED_RESET - s_axi_intr_aresetn - - - S00_AXI_RST @@ -477,26 +231,6 @@ - - S_AXI_INTR - - S_AXI_INTR_reg - 0 - 4096 - 32 - register - - - OFFSET_BASE_PARAM - 0 - - - OFFSET_HIGH_PARAM - 0 - - - - S00_AXI @@ -520,26 +254,6 @@ - - xilinx_vhdlsynthesis - VHDL Synthesis - vhdlSource:vivado.xilinx.com:synthesis - vhdl - sja1000_v1_0 - - xilinx_vhdlsynthesis_view_fileset - - - - xilinx_vhdlbehavioralsimulation - VHDL Simulation - vhdlSource:vivado.xilinx.com:simulation - vhdl - sja1000_v1_0 - - xilinx_vhdlbehavioralsimulation_view_fileset - - xilinx_softwaredriver Software Driver @@ -547,6 +261,12 @@ xilinx_softwaredriver_view_fileset + + + viewChecksum + a7e67acd + + xilinx_xpgui @@ -555,6 +275,12 @@ xilinx_xpgui_view_fileset + + + viewChecksum + fd592ead + + bd_tcl @@ -563,327 +289,93 @@ bd_tcl_view_fileset + + + viewChecksum + 45a2f450 + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + sja1000 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 4030548c + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + sja1000 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 4030548c + + - s_axi_intr_awaddr - - in - - 4 - 0 - - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_awprot - - in - - 2 - 0 - - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_awvalid - - in - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_awready - - out - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_wdata - - in - - 31 - 0 - - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_wstrb - - in - - 3 - 0 - - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_wvalid - - in - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_wready - - out - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_bresp - - out - - 1 - 0 - - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_bvalid - - out - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_bready - - in - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_araddr - - in - - 4 - 0 - - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_arprot + can_clk in - - 2 - 0 - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation - s_axi_intr_arvalid + can_rx in wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_arready - - out - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_rdata - - out - - 31 - 0 - - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_rresp - - out - - 1 - 0 - - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation - s_axi_intr_rvalid + can_tx out wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_rready - - in - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_aclk - - in - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation - - - - - - s_axi_intr_aresetn - - in - - - wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation - irq + bus_off_on out wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -893,14 +385,14 @@ in - 9 + 7 0 wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -916,8 +408,8 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -929,8 +421,8 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -942,8 +434,8 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -953,14 +445,14 @@ in - 31 + 31 0 wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -970,14 +462,14 @@ in - 3 + 3 0 wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -989,8 +481,8 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -1002,8 +494,8 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -1019,8 +511,8 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -1032,8 +524,8 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -1045,8 +537,8 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -1056,14 +548,14 @@ in - 9 + 7 0 wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -1079,8 +571,8 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -1092,8 +584,8 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -1105,8 +597,8 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -1116,14 +608,14 @@ out - 31 + 31 0 wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -1139,8 +631,8 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -1152,8 +644,8 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -1165,8 +657,21 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + irq + + out + + + wire + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -1178,8 +683,8 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -1191,8 +696,8 @@ wire - xilinx_vhdlsynthesis - xilinx_vhdlbehavioralsimulation + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation @@ -1200,64 +705,22 @@ - C_S_AXI_INTR_DATA_WIDTH - C S AXI INTR DATA WIDTH - Width of S_AXI data bus - 32 - - - C_S_AXI_INTR_ADDR_WIDTH - C S AXI INTR ADDR WIDTH - Width of S_AXI address bus - 5 - - - C_NUM_OF_INTR - C NUM OF INTR - Number of Interrupts - 1 - - - C_INTR_SENSITIVITY - C INTR SENSITIVITY - Each bit corresponds to Sensitivity of interrupt : 0 - EDGE, 1 - LEVEL - 0xFFFFFFFF - - - C_INTR_ACTIVE_STATE - C INTR ACTIVE STATE - Each bit corresponds to Sub-type of INTR: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_INTR_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_INTR_SENSITIVITY is LEVEL(1) ] - 0xFFFFFFFF - - - C_IRQ_SENSITIVITY - C IRQ SENSITIVITY - Sensitivity of IRQ: 0 - EDGE, 1 - LEVEL - 1 - - - C_IRQ_ACTIVE_STATE - C IRQ ACTIVE STATE - Sub-type of IRQ: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_IRQ_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_IRQ_SENSITIVITY is LEVEL(1) ] - 1 - - C_S00_AXI_DATA_WIDTH C S00 AXI DATA WIDTH Width of S_AXI data bus - 32 + 32 C_S00_AXI_ADDR_WIDTH C S00 AXI ADDR WIDTH Width of S_AXI address bus - 10 + 8 - choice_list_ea018de4 + choice_list_6fc15197 32 @@ -1267,40 +730,6 @@ - - xilinx_vhdlsynthesis_view_fileset - - hdl/sja1000_v1_0_S00_AXI.vhd - vhdlSource - - - hdl/sja1000_v1_0_S_AXI_INTR.vhd - vhdlSource - - - hdl/sja1000_v1_0.vhd - vhdlSource - CHECKSUM_c0f4fbf5 - - - - xilinx_vhdlbehavioralsimulation_view_fileset - - hdl/sja1000_v1_0_S00_AXI.vhd - vhdlSource - USED_IN_ipstatic - - - hdl/sja1000_v1_0_S_AXI_INTR.vhd - vhdlSource - USED_IN_ipstatic - - - hdl/sja1000_v1_0.vhd - vhdlSource - USED_IN_ipstatic - - xilinx_softwaredriver_view_fileset @@ -1338,7 +767,7 @@ xgui/sja1000_v1_0.tcl tclSource - CHECKSUM_9907a0a4 + CHECKSUM_fd592ead XGUI_VERSION_2 @@ -1349,94 +778,197 @@ tclSource + + xilinx_anylanguagesynthesis_view_fileset + + hdl/can_crc.v + verilogSource + xil_defaultlib + + + hdl/can_register_asyn_syn.v + verilogSource + xil_defaultlib + + + hdl/can_fifo.v + verilogSource + xil_defaultlib + + + hdl/can_register_syn.v + verilogSource + xil_defaultlib + + + hdl/can_defines.v + verilogSource + xil_defaultlib + + + hdl/can_btl.v + verilogSource + xil_defaultlib + + + hdl/timescale.v + verilogSource + xil_defaultlib + + + hdl/can_bsp.v + verilogSource + xil_defaultlib + + + hdl/can_registers.v + verilogSource + xil_defaultlib + + + hdl/can_register_asyn.v + verilogSource + xil_defaultlib + + + hdl/sja1000.v + verilogSource + xil_defaultlib + + + hdl/can_top_raw.v + verilogSource + xil_defaultlib + + + hdl/can_ibo.v + verilogSource + xil_defaultlib + + + hdl/can_acf.v + verilogSource + xil_defaultlib + + + hdl/can_ifc_axi.v + verilogSource + xil_defaultlib + + + hdl/can_register.v + verilogSource + CHECKSUM_afda1032 + xil_defaultlib + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/can_crc.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/can_register_asyn_syn.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/can_fifo.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/can_register_syn.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/can_defines.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/can_btl.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/timescale.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/can_bsp.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/can_registers.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/can_register_asyn.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/sja1000.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/can_top_raw.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/can_ibo.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/can_acf.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/can_ifc_axi.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + + hdl/can_register.v + verilogSource + USED_IN_ipstatic + xil_defaultlib + + SJA1000 Soft Core - - C_S_AXI_INTR_DATA_WIDTH - C S AXI INTR DATA WIDTH - Width of S_AXI data bus - 32 - - - - false - - - - - - C_S_AXI_INTR_ADDR_WIDTH - C S AXI INTR ADDR WIDTH - Width of S_AXI address bus - 5 - - - - false - - - - - - C_NUM_OF_INTR - C NUM OF INTR - Number of Interrupts - 1 - - - C_INTR_SENSITIVITY - C INTR SENSITIVITY - Each bit corresponds to Sensitivity of interrupt : 0 - EDGE, 1 - LEVEL - 0xFFFFFFFF - - - C_INTR_ACTIVE_STATE - C INTR ACTIVE STATE - Each bit corresponds to Sub-type of INTR: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_INTR_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_INTR_SENSITIVITY is LEVEL(1) ] - 0xFFFFFFFF - - - C_IRQ_SENSITIVITY - C IRQ SENSITIVITY - Sensitivity of IRQ: 0 - EDGE, 1 - LEVEL - 1 - - - C_IRQ_ACTIVE_STATE - C IRQ ACTIVE STATE - Sub-type of IRQ: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_IRQ_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_IRQ_SENSITIVITY is LEVEL(1) ] - 1 - - - C_S_AXI_INTR_BASEADDR - C S AXI INTR BASEADDR - 0xFFFFFFFF - - - - false - - - - - - C_S_AXI_INTR_HIGHADDR - C S AXI INTR HIGHADDR - 0x00000000 - - - - false - - - - C_S00_AXI_DATA_WIDTH C S00 AXI DATA WIDTH Width of S_AXI data bus - 32 + 32 @@ -1449,7 +981,7 @@ C_S00_AXI_ADDR_WIDTH C S00 AXI ADDR WIDTH Width of S_AXI address bus - 10 + 8 @@ -1461,26 +993,12 @@ C_S00_AXI_BASEADDR C S00 AXI BASEADDR - 0xFFFFFFFF - - - - false - - - + 0xFFFFFFFF C_S00_AXI_HIGHADDR C S00 AXI HIGHADDR - 0x00000000 - - - - false - - - + 0x00000000 Component_Name @@ -1496,11 +1014,20 @@ AXI_Peripheral sja1000_v1.0 - 1 - 2016-05-08T23:03:05Z + 3 + 2016-05-11T10:03:38Z + + /home/martin/projects/cvut/bakalarka/canbench-sw/system/ip/sja1000_1.0 + 2015.4 + + + + + + diff --git a/system/ip/sja1000_1.0/drivers/sja1000_v1_0/src/Makefile b/system/ip/sja1000_1.0/drivers/sja1000_v1_0/src/Makefile new file mode 100644 index 0000000..8d379be --- /dev/null +++ b/system/ip/sja1000_1.0/drivers/sja1000_v1_0/src/Makefile @@ -0,0 +1,26 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + +libs: + echo "Compiling sja1000..." + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + make clean + +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OUTS} diff --git a/system/ip/sja1000_1.0/drivers/sja1000_v1_0/src/sja1000.c b/system/ip/sja1000_1.0/drivers/sja1000_v1_0/src/sja1000.c new file mode 100644 index 0000000..6bcf59c --- /dev/null +++ b/system/ip/sja1000_1.0/drivers/sja1000_v1_0/src/sja1000.c @@ -0,0 +1,6 @@ + + +/***************************** Include Files *******************************/ +#include "sja1000.h" + +/************************** Function Definitions ***************************/ diff --git a/system/ip/sja1000_1.0/drivers/sja1000_v1_0/src/sja1000.h b/system/ip/sja1000_1.0/drivers/sja1000_v1_0/src/sja1000.h new file mode 100644 index 0000000..a386248 --- /dev/null +++ b/system/ip/sja1000_1.0/drivers/sja1000_v1_0/src/sja1000.h @@ -0,0 +1,330 @@ + +#ifndef SJA1000_H +#define SJA1000_H + + +/****************** Include Files ********************/ +#include "xil_types.h" +#include "xstatus.h" + +#define SJA1000_S00_AXI_SLV_REG0_OFFSET 0 +#define SJA1000_S00_AXI_SLV_REG1_OFFSET 4 +#define SJA1000_S00_AXI_SLV_REG2_OFFSET 8 +#define SJA1000_S00_AXI_SLV_REG3_OFFSET 12 +#define SJA1000_S00_AXI_SLV_REG4_OFFSET 16 +#define SJA1000_S00_AXI_SLV_REG5_OFFSET 20 +#define SJA1000_S00_AXI_SLV_REG6_OFFSET 24 +#define SJA1000_S00_AXI_SLV_REG7_OFFSET 28 +#define SJA1000_S00_AXI_SLV_REG8_OFFSET 32 +#define SJA1000_S00_AXI_SLV_REG9_OFFSET 36 +#define SJA1000_S00_AXI_SLV_REG10_OFFSET 40 +#define SJA1000_S00_AXI_SLV_REG11_OFFSET 44 +#define SJA1000_S00_AXI_SLV_REG12_OFFSET 48 +#define SJA1000_S00_AXI_SLV_REG13_OFFSET 52 +#define SJA1000_S00_AXI_SLV_REG14_OFFSET 56 +#define SJA1000_S00_AXI_SLV_REG15_OFFSET 60 +#define SJA1000_S00_AXI_SLV_REG16_OFFSET 64 +#define SJA1000_S00_AXI_SLV_REG17_OFFSET 68 +#define SJA1000_S00_AXI_SLV_REG18_OFFSET 72 +#define SJA1000_S00_AXI_SLV_REG19_OFFSET 76 +#define SJA1000_S00_AXI_SLV_REG20_OFFSET 80 +#define SJA1000_S00_AXI_SLV_REG21_OFFSET 84 +#define SJA1000_S00_AXI_SLV_REG22_OFFSET 88 +#define SJA1000_S00_AXI_SLV_REG23_OFFSET 92 +#define SJA1000_S00_AXI_SLV_REG24_OFFSET 96 +#define SJA1000_S00_AXI_SLV_REG25_OFFSET 100 +#define SJA1000_S00_AXI_SLV_REG26_OFFSET 104 +#define SJA1000_S00_AXI_SLV_REG27_OFFSET 108 +#define SJA1000_S00_AXI_SLV_REG28_OFFSET 112 +#define SJA1000_S00_AXI_SLV_REG29_OFFSET 116 +#define SJA1000_S00_AXI_SLV_REG30_OFFSET 120 +#define SJA1000_S00_AXI_SLV_REG31_OFFSET 124 +#define SJA1000_S00_AXI_SLV_REG32_OFFSET 128 +#define SJA1000_S00_AXI_SLV_REG33_OFFSET 132 +#define SJA1000_S00_AXI_SLV_REG34_OFFSET 136 +#define SJA1000_S00_AXI_SLV_REG35_OFFSET 140 +#define SJA1000_S00_AXI_SLV_REG36_OFFSET 144 +#define SJA1000_S00_AXI_SLV_REG37_OFFSET 148 +#define SJA1000_S00_AXI_SLV_REG38_OFFSET 152 +#define SJA1000_S00_AXI_SLV_REG39_OFFSET 156 +#define SJA1000_S00_AXI_SLV_REG40_OFFSET 160 +#define SJA1000_S00_AXI_SLV_REG41_OFFSET 164 +#define SJA1000_S00_AXI_SLV_REG42_OFFSET 168 +#define SJA1000_S00_AXI_SLV_REG43_OFFSET 172 +#define SJA1000_S00_AXI_SLV_REG44_OFFSET 176 +#define SJA1000_S00_AXI_SLV_REG45_OFFSET 180 +#define SJA1000_S00_AXI_SLV_REG46_OFFSET 184 +#define SJA1000_S00_AXI_SLV_REG47_OFFSET 188 +#define SJA1000_S00_AXI_SLV_REG48_OFFSET 192 +#define SJA1000_S00_AXI_SLV_REG49_OFFSET 196 +#define SJA1000_S00_AXI_SLV_REG50_OFFSET 200 +#define SJA1000_S00_AXI_SLV_REG51_OFFSET 204 +#define SJA1000_S00_AXI_SLV_REG52_OFFSET 208 +#define SJA1000_S00_AXI_SLV_REG53_OFFSET 212 +#define SJA1000_S00_AXI_SLV_REG54_OFFSET 216 +#define SJA1000_S00_AXI_SLV_REG55_OFFSET 220 +#define SJA1000_S00_AXI_SLV_REG56_OFFSET 224 +#define SJA1000_S00_AXI_SLV_REG57_OFFSET 228 +#define SJA1000_S00_AXI_SLV_REG58_OFFSET 232 +#define SJA1000_S00_AXI_SLV_REG59_OFFSET 236 +#define SJA1000_S00_AXI_SLV_REG60_OFFSET 240 +#define SJA1000_S00_AXI_SLV_REG61_OFFSET 244 +#define SJA1000_S00_AXI_SLV_REG62_OFFSET 248 +#define SJA1000_S00_AXI_SLV_REG63_OFFSET 252 +#define SJA1000_S00_AXI_SLV_REG64_OFFSET 256 +#define SJA1000_S00_AXI_SLV_REG65_OFFSET 260 +#define SJA1000_S00_AXI_SLV_REG66_OFFSET 264 +#define SJA1000_S00_AXI_SLV_REG67_OFFSET 268 +#define SJA1000_S00_AXI_SLV_REG68_OFFSET 272 +#define SJA1000_S00_AXI_SLV_REG69_OFFSET 276 +#define SJA1000_S00_AXI_SLV_REG70_OFFSET 280 +#define SJA1000_S00_AXI_SLV_REG71_OFFSET 284 +#define SJA1000_S00_AXI_SLV_REG72_OFFSET 288 +#define SJA1000_S00_AXI_SLV_REG73_OFFSET 292 +#define SJA1000_S00_AXI_SLV_REG74_OFFSET 296 +#define SJA1000_S00_AXI_SLV_REG75_OFFSET 300 +#define SJA1000_S00_AXI_SLV_REG76_OFFSET 304 +#define SJA1000_S00_AXI_SLV_REG77_OFFSET 308 +#define SJA1000_S00_AXI_SLV_REG78_OFFSET 312 +#define SJA1000_S00_AXI_SLV_REG79_OFFSET 316 +#define SJA1000_S00_AXI_SLV_REG80_OFFSET 320 +#define SJA1000_S00_AXI_SLV_REG81_OFFSET 324 +#define SJA1000_S00_AXI_SLV_REG82_OFFSET 328 +#define SJA1000_S00_AXI_SLV_REG83_OFFSET 332 +#define SJA1000_S00_AXI_SLV_REG84_OFFSET 336 +#define SJA1000_S00_AXI_SLV_REG85_OFFSET 340 +#define SJA1000_S00_AXI_SLV_REG86_OFFSET 344 +#define SJA1000_S00_AXI_SLV_REG87_OFFSET 348 +#define SJA1000_S00_AXI_SLV_REG88_OFFSET 352 +#define SJA1000_S00_AXI_SLV_REG89_OFFSET 356 +#define SJA1000_S00_AXI_SLV_REG90_OFFSET 360 +#define SJA1000_S00_AXI_SLV_REG91_OFFSET 364 +#define SJA1000_S00_AXI_SLV_REG92_OFFSET 368 +#define SJA1000_S00_AXI_SLV_REG93_OFFSET 372 +#define SJA1000_S00_AXI_SLV_REG94_OFFSET 376 +#define SJA1000_S00_AXI_SLV_REG95_OFFSET 380 +#define SJA1000_S00_AXI_SLV_REG96_OFFSET 384 +#define SJA1000_S00_AXI_SLV_REG97_OFFSET 388 +#define SJA1000_S00_AXI_SLV_REG98_OFFSET 392 +#define SJA1000_S00_AXI_SLV_REG99_OFFSET 396 +#define SJA1000_S00_AXI_SLV_REG100_OFFSET 400 +#define SJA1000_S00_AXI_SLV_REG101_OFFSET 404 +#define SJA1000_S00_AXI_SLV_REG102_OFFSET 408 +#define SJA1000_S00_AXI_SLV_REG103_OFFSET 412 +#define SJA1000_S00_AXI_SLV_REG104_OFFSET 416 +#define SJA1000_S00_AXI_SLV_REG105_OFFSET 420 +#define SJA1000_S00_AXI_SLV_REG106_OFFSET 424 +#define SJA1000_S00_AXI_SLV_REG107_OFFSET 428 +#define SJA1000_S00_AXI_SLV_REG108_OFFSET 432 +#define SJA1000_S00_AXI_SLV_REG109_OFFSET 436 +#define SJA1000_S00_AXI_SLV_REG110_OFFSET 440 +#define SJA1000_S00_AXI_SLV_REG111_OFFSET 444 +#define SJA1000_S00_AXI_SLV_REG112_OFFSET 448 +#define SJA1000_S00_AXI_SLV_REG113_OFFSET 452 +#define SJA1000_S00_AXI_SLV_REG114_OFFSET 456 +#define SJA1000_S00_AXI_SLV_REG115_OFFSET 460 +#define SJA1000_S00_AXI_SLV_REG116_OFFSET 464 +#define SJA1000_S00_AXI_SLV_REG117_OFFSET 468 +#define SJA1000_S00_AXI_SLV_REG118_OFFSET 472 +#define SJA1000_S00_AXI_SLV_REG119_OFFSET 476 +#define SJA1000_S00_AXI_SLV_REG120_OFFSET 480 +#define SJA1000_S00_AXI_SLV_REG121_OFFSET 484 +#define SJA1000_S00_AXI_SLV_REG122_OFFSET 488 +#define SJA1000_S00_AXI_SLV_REG123_OFFSET 492 +#define SJA1000_S00_AXI_SLV_REG124_OFFSET 496 +#define SJA1000_S00_AXI_SLV_REG125_OFFSET 500 +#define SJA1000_S00_AXI_SLV_REG126_OFFSET 504 +#define SJA1000_S00_AXI_SLV_REG127_OFFSET 508 +#define SJA1000_S00_AXI_SLV_REG128_OFFSET 512 +#define SJA1000_S00_AXI_SLV_REG129_OFFSET 516 +#define SJA1000_S00_AXI_SLV_REG130_OFFSET 520 +#define SJA1000_S00_AXI_SLV_REG131_OFFSET 524 +#define SJA1000_S00_AXI_SLV_REG132_OFFSET 528 +#define SJA1000_S00_AXI_SLV_REG133_OFFSET 532 +#define SJA1000_S00_AXI_SLV_REG134_OFFSET 536 +#define SJA1000_S00_AXI_SLV_REG135_OFFSET 540 +#define SJA1000_S00_AXI_SLV_REG136_OFFSET 544 +#define SJA1000_S00_AXI_SLV_REG137_OFFSET 548 +#define SJA1000_S00_AXI_SLV_REG138_OFFSET 552 +#define SJA1000_S00_AXI_SLV_REG139_OFFSET 556 +#define SJA1000_S00_AXI_SLV_REG140_OFFSET 560 +#define SJA1000_S00_AXI_SLV_REG141_OFFSET 564 +#define SJA1000_S00_AXI_SLV_REG142_OFFSET 568 +#define SJA1000_S00_AXI_SLV_REG143_OFFSET 572 +#define SJA1000_S00_AXI_SLV_REG144_OFFSET 576 +#define SJA1000_S00_AXI_SLV_REG145_OFFSET 580 +#define SJA1000_S00_AXI_SLV_REG146_OFFSET 584 +#define SJA1000_S00_AXI_SLV_REG147_OFFSET 588 +#define SJA1000_S00_AXI_SLV_REG148_OFFSET 592 +#define SJA1000_S00_AXI_SLV_REG149_OFFSET 596 +#define SJA1000_S00_AXI_SLV_REG150_OFFSET 600 +#define SJA1000_S00_AXI_SLV_REG151_OFFSET 604 +#define SJA1000_S00_AXI_SLV_REG152_OFFSET 608 +#define SJA1000_S00_AXI_SLV_REG153_OFFSET 612 +#define SJA1000_S00_AXI_SLV_REG154_OFFSET 616 +#define SJA1000_S00_AXI_SLV_REG155_OFFSET 620 +#define SJA1000_S00_AXI_SLV_REG156_OFFSET 624 +#define SJA1000_S00_AXI_SLV_REG157_OFFSET 628 +#define SJA1000_S00_AXI_SLV_REG158_OFFSET 632 +#define SJA1000_S00_AXI_SLV_REG159_OFFSET 636 +#define SJA1000_S00_AXI_SLV_REG160_OFFSET 640 +#define SJA1000_S00_AXI_SLV_REG161_OFFSET 644 +#define SJA1000_S00_AXI_SLV_REG162_OFFSET 648 +#define SJA1000_S00_AXI_SLV_REG163_OFFSET 652 +#define SJA1000_S00_AXI_SLV_REG164_OFFSET 656 +#define SJA1000_S00_AXI_SLV_REG165_OFFSET 660 +#define SJA1000_S00_AXI_SLV_REG166_OFFSET 664 +#define SJA1000_S00_AXI_SLV_REG167_OFFSET 668 +#define SJA1000_S00_AXI_SLV_REG168_OFFSET 672 +#define SJA1000_S00_AXI_SLV_REG169_OFFSET 676 +#define SJA1000_S00_AXI_SLV_REG170_OFFSET 680 +#define SJA1000_S00_AXI_SLV_REG171_OFFSET 684 +#define SJA1000_S00_AXI_SLV_REG172_OFFSET 688 +#define SJA1000_S00_AXI_SLV_REG173_OFFSET 692 +#define SJA1000_S00_AXI_SLV_REG174_OFFSET 696 +#define SJA1000_S00_AXI_SLV_REG175_OFFSET 700 +#define SJA1000_S00_AXI_SLV_REG176_OFFSET 704 +#define SJA1000_S00_AXI_SLV_REG177_OFFSET 708 +#define SJA1000_S00_AXI_SLV_REG178_OFFSET 712 +#define SJA1000_S00_AXI_SLV_REG179_OFFSET 716 +#define SJA1000_S00_AXI_SLV_REG180_OFFSET 720 +#define SJA1000_S00_AXI_SLV_REG181_OFFSET 724 +#define SJA1000_S00_AXI_SLV_REG182_OFFSET 728 +#define SJA1000_S00_AXI_SLV_REG183_OFFSET 732 +#define SJA1000_S00_AXI_SLV_REG184_OFFSET 736 +#define SJA1000_S00_AXI_SLV_REG185_OFFSET 740 +#define SJA1000_S00_AXI_SLV_REG186_OFFSET 744 +#define SJA1000_S00_AXI_SLV_REG187_OFFSET 748 +#define SJA1000_S00_AXI_SLV_REG188_OFFSET 752 +#define SJA1000_S00_AXI_SLV_REG189_OFFSET 756 +#define SJA1000_S00_AXI_SLV_REG190_OFFSET 760 +#define SJA1000_S00_AXI_SLV_REG191_OFFSET 764 +#define SJA1000_S00_AXI_SLV_REG192_OFFSET 768 +#define SJA1000_S00_AXI_SLV_REG193_OFFSET 772 +#define SJA1000_S00_AXI_SLV_REG194_OFFSET 776 +#define SJA1000_S00_AXI_SLV_REG195_OFFSET 780 +#define SJA1000_S00_AXI_SLV_REG196_OFFSET 784 +#define SJA1000_S00_AXI_SLV_REG197_OFFSET 788 +#define SJA1000_S00_AXI_SLV_REG198_OFFSET 792 +#define SJA1000_S00_AXI_SLV_REG199_OFFSET 796 +#define SJA1000_S00_AXI_SLV_REG200_OFFSET 800 +#define SJA1000_S00_AXI_SLV_REG201_OFFSET 804 +#define SJA1000_S00_AXI_SLV_REG202_OFFSET 808 +#define SJA1000_S00_AXI_SLV_REG203_OFFSET 812 +#define SJA1000_S00_AXI_SLV_REG204_OFFSET 816 +#define SJA1000_S00_AXI_SLV_REG205_OFFSET 820 +#define SJA1000_S00_AXI_SLV_REG206_OFFSET 824 +#define SJA1000_S00_AXI_SLV_REG207_OFFSET 828 +#define SJA1000_S00_AXI_SLV_REG208_OFFSET 832 +#define SJA1000_S00_AXI_SLV_REG209_OFFSET 836 +#define SJA1000_S00_AXI_SLV_REG210_OFFSET 840 +#define SJA1000_S00_AXI_SLV_REG211_OFFSET 844 +#define SJA1000_S00_AXI_SLV_REG212_OFFSET 848 +#define SJA1000_S00_AXI_SLV_REG213_OFFSET 852 +#define SJA1000_S00_AXI_SLV_REG214_OFFSET 856 +#define SJA1000_S00_AXI_SLV_REG215_OFFSET 860 +#define SJA1000_S00_AXI_SLV_REG216_OFFSET 864 +#define SJA1000_S00_AXI_SLV_REG217_OFFSET 868 +#define SJA1000_S00_AXI_SLV_REG218_OFFSET 872 +#define SJA1000_S00_AXI_SLV_REG219_OFFSET 876 +#define SJA1000_S00_AXI_SLV_REG220_OFFSET 880 +#define SJA1000_S00_AXI_SLV_REG221_OFFSET 884 +#define SJA1000_S00_AXI_SLV_REG222_OFFSET 888 +#define SJA1000_S00_AXI_SLV_REG223_OFFSET 892 +#define SJA1000_S00_AXI_SLV_REG224_OFFSET 896 +#define SJA1000_S00_AXI_SLV_REG225_OFFSET 900 +#define SJA1000_S00_AXI_SLV_REG226_OFFSET 904 +#define SJA1000_S00_AXI_SLV_REG227_OFFSET 908 +#define SJA1000_S00_AXI_SLV_REG228_OFFSET 912 +#define SJA1000_S00_AXI_SLV_REG229_OFFSET 916 +#define SJA1000_S00_AXI_SLV_REG230_OFFSET 920 +#define SJA1000_S00_AXI_SLV_REG231_OFFSET 924 +#define SJA1000_S00_AXI_SLV_REG232_OFFSET 928 +#define SJA1000_S00_AXI_SLV_REG233_OFFSET 932 +#define SJA1000_S00_AXI_SLV_REG234_OFFSET 936 +#define SJA1000_S00_AXI_SLV_REG235_OFFSET 940 +#define SJA1000_S00_AXI_SLV_REG236_OFFSET 944 +#define SJA1000_S00_AXI_SLV_REG237_OFFSET 948 +#define SJA1000_S00_AXI_SLV_REG238_OFFSET 952 +#define SJA1000_S00_AXI_SLV_REG239_OFFSET 956 +#define SJA1000_S00_AXI_SLV_REG240_OFFSET 960 +#define SJA1000_S00_AXI_SLV_REG241_OFFSET 964 +#define SJA1000_S00_AXI_SLV_REG242_OFFSET 968 +#define SJA1000_S00_AXI_SLV_REG243_OFFSET 972 +#define SJA1000_S00_AXI_SLV_REG244_OFFSET 976 +#define SJA1000_S00_AXI_SLV_REG245_OFFSET 980 +#define SJA1000_S00_AXI_SLV_REG246_OFFSET 984 +#define SJA1000_S00_AXI_SLV_REG247_OFFSET 988 +#define SJA1000_S00_AXI_SLV_REG248_OFFSET 992 +#define SJA1000_S00_AXI_SLV_REG249_OFFSET 996 +#define SJA1000_S00_AXI_SLV_REG250_OFFSET 1000 +#define SJA1000_S00_AXI_SLV_REG251_OFFSET 1004 +#define SJA1000_S00_AXI_SLV_REG252_OFFSET 1008 +#define SJA1000_S00_AXI_SLV_REG253_OFFSET 1012 +#define SJA1000_S00_AXI_SLV_REG254_OFFSET 1016 + + +/**************************** Type Definitions *****************************/ +/** + * + * Write a value to a SJA1000 register. A 32 bit write is performed. + * If the component is implemented in a smaller width, only the least + * significant data is written. + * + * @param BaseAddress is the base address of the SJA1000device. + * @param RegOffset is the register offset from the base to write to. + * @param Data is the data written to the register. + * + * @return None. + * + * @note + * C-style signature: + * void SJA1000_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) + * + */ +#define SJA1000_mWriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/** + * + * Read a value from a SJA1000 register. A 32 bit read is performed. + * If the component is implemented in a smaller width, only the least + * significant data is read from the register. The most significant data + * will be read as 0. + * + * @param BaseAddress is the base address of the SJA1000 device. + * @param RegOffset is the register offset from the base to write to. + * + * @return Data is the data from the register. + * + * @note + * C-style signature: + * u32 SJA1000_mReadReg(u32 BaseAddress, unsigned RegOffset) + * + */ +#define SJA1000_mReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/************************** Function Prototypes ****************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the SJA1000 instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus SJA1000_Reg_SelfTest(void * baseaddr_p); + +#endif // SJA1000_H diff --git a/system/ip/sja1000_1.0/drivers/sja1000_v1_0/src/sja1000_selftest.c b/system/ip/sja1000_1.0/drivers/sja1000_v1_0/src/sja1000_selftest.c new file mode 100644 index 0000000..963f8f5 --- /dev/null +++ b/system/ip/sja1000_1.0/drivers/sja1000_v1_0/src/sja1000_selftest.c @@ -0,0 +1,60 @@ + +/***************************** Include Files *******************************/ +#include "sja1000.h" +#include "xparameters.h" +#include "stdio.h" +#include "xil_io.h" + +/************************** Constant Definitions ***************************/ +#define READ_WRITE_MUL_FACTOR 0x10 + +/************************** Function Definitions ***************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the SJA1000instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus SJA1000_Reg_SelfTest(void * baseaddr_p) +{ + u32 baseaddr; + int write_loop_index; + int read_loop_index; + int Index; + + baseaddr = (u32) baseaddr_p; + + xil_printf("******************************\n\r"); + xil_printf("* User Peripheral Self Test\n\r"); + xil_printf("******************************\n\n\r"); + + /* + * Write to user logic slave module register(s) and read back + */ + xil_printf("User logic slave module test...\n\r"); + + for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) + SJA1000_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); + for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) + if ( SJA1000_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ + xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); + return XST_FAILURE; + } + + xil_printf(" - slave register write/read passed\n\n\r"); + + return XST_SUCCESS; +} diff --git a/system/ip/sja1000_1.0/example_designs/bfm_design/design.tcl b/system/ip/sja1000_1.0/example_designs/bfm_design/design.tcl new file mode 100644 index 0000000..d468880 --- /dev/null +++ b/system/ip/sja1000_1.0/example_designs/bfm_design/design.tcl @@ -0,0 +1,91 @@ +proc create_ipi_design { offsetfile design_name } { + create_bd_design $design_name + open_bd_design $design_name + + # Create Clock and Reset Ports + set ACLK [ create_bd_port -dir I -type clk ACLK ] + set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK + set ARESETN [ create_bd_port -dir I -type rst ARESETN ] + set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN + set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK + + # Create instance: sja1000_0, and set properties + set sja1000_0 [ create_bd_cell -type ip -vlnv user.org:user:sja1000:1.0 sja1000_0] + + # Create instance: master_0, and set properties + set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm master_0] + set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {2} ] $master_0 + + # Create interface connections + connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI_LITE] [get_bd_intf_pins sja1000_0/S00_AXI] + + # Create port connections + connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/M_AXI_LITE_ACLK] [get_bd_pins sja1000_0/S00_AXI_ACLK] + connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/M_AXI_LITE_ARESETN] [get_bd_pins sja1000_0/S00_AXI_ARESETN] + + # Auto assign address + assign_bd_address + + # Copy all address to interface_address.vh file + set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]] + upvar 1 $offsetfile offset_file + set offset_file "${bd_path}/sja1000_v1_0_tb_include.vh" + set fp [open $offset_file "w"] + puts $fp "`ifndef sja1000_v1_0_tb_include_vh_" + puts $fp "`define sja1000_v1_0_tb_include_vh_\n" + puts $fp "//Configuration current bd names" + puts $fp "`define BD_INST_NAME ${design_name}_i" + puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n" + puts $fp "//Configuration address parameters" + + set offset [get_property OFFSET [get_bd_addr_segs -of_objects [get_bd_addr_spaces master_0/Data_lite]]] + set offset_hex [string replace $offset 0 1 "32'h"] + puts $fp "`define S00_AXI_SLAVE_ADDRESS ${offset_hex}" + + puts $fp "`endif" + close $fp +} + +set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:sja1000:1.0]]]] +set test_bench_file ${ip_path}/example_designs/bfm_design/sja1000_v1_0_tb.v +set interface_address_vh_file "" + +# Set IP Repository and Update IP Catalogue +set repo_paths [get_property ip_repo_paths [current_fileset]] +if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { + set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] + update_ip_catalog +} + +set design_name "" +set all_bd {} +set all_bd_files [get_files *.bd -quiet] +foreach file $all_bd_files { +set file_name [string range $file [expr {[string last "/" $file] + 1}] end] +set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] +lappend all_bd $bd_name +} + +for { set i 1 } { 1 } { incr i } { + set design_name "sja1000_v1_0_bfm_${i}" + if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { + break + } +} + +create_ipi_design interface_address_vh_file ${design_name} +validate_bd_design + +set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] +import_files -force -norecurse $wrapper_file + +set_property SOURCE_SET sources_1 [get_filesets sim_1] +import_files -fileset sim_1 -norecurse -force $test_bench_file +remove_files -quiet -fileset sim_1 sja1000_v1_0_tb_include.vh +import_files -fileset sim_1 -norecurse -force $interface_address_vh_file +set_property top sja1000_v1_0_tb [get_filesets sim_1] +set_property top_lib {} [get_filesets sim_1] +set_property top_file {} [get_filesets sim_1] +launch_xsim -simset sim_1 -mode behavioral +restart +run 1000 us diff --git a/system/ip/sja1000_1.0/example_designs/bfm_design/sja1000_v1_0_tb.v b/system/ip/sja1000_1.0/example_designs/bfm_design/sja1000_v1_0_tb.v new file mode 100644 index 0000000..7195cb0 --- /dev/null +++ b/system/ip/sja1000_1.0/example_designs/bfm_design/sja1000_v1_0_tb.v @@ -0,0 +1,185 @@ + +`timescale 1 ns / 1 ps + +`include "sja1000_v1_0_tb_include.vh" + +// lite_response Type Defines +`define RESPONSE_OKAY 2'b00 +`define RESPONSE_EXOKAY 2'b01 +`define RESP_BUS_WIDTH 2 +`define BURST_TYPE_INCR 2'b01 +`define BURST_TYPE_WRAP 2'b10 + +// AMBA AXI4 Lite Range Constants +`define S00_AXI_MAX_BURST_LENGTH 1 +`define S00_AXI_DATA_BUS_WIDTH 32 +`define S00_AXI_ADDRESS_BUS_WIDTH 32 +`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8 + +module sja1000_v1_0_tb; + reg tb_ACLK; + reg tb_ARESETn; + + // Create an instance of the example tb + `BD_WRAPPER dut (.ACLK(tb_ACLK), + .ARESETN(tb_ARESETn)); + + // Local Variables + + // AMBA S00_AXI AXI4 Lite Local Reg + reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite; + reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0]; + reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response; + reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress; + reg [3-1:0] S00_AXI_mtestProtection_lite; + integer S00_AXI_mtestvectorlite; // Master side testvector + integer S00_AXI_mtestdatasizelite; + integer result_slave_lite; + + + // Simple Reset Generator and test + initial begin + tb_ARESETn = 1'b0; + #500; + // Release the reset on the posedge of the clk. + @(posedge tb_ACLK); + tb_ARESETn = 1'b1; + @(posedge tb_ACLK); + end + + // Simple Clock Generator + initial tb_ACLK = 1'b0; + always #10 tb_ACLK = !tb_ACLK; + + //------------------------------------------------------------------------ + // TEST LEVEL API: CHECK_RESPONSE_OKAY + //------------------------------------------------------------------------ + // Description: + // CHECK_RESPONSE_OKAY(lite_response) + // This task checks if the return lite_response is equal to OKAY + //------------------------------------------------------------------------ + task automatic CHECK_RESPONSE_OKAY; + input [`RESP_BUS_WIDTH-1:0] response; + begin + if (response !== `RESPONSE_OKAY) begin + $display("TESTBENCH ERROR! lite_response is not OKAY", + "\n expected = 0x%h",`RESPONSE_OKAY, + "\n actual = 0x%h",response); + $stop; + end + end + endtask + + //------------------------------------------------------------------------ + // TEST LEVEL API: COMPARE_LITE_DATA + //------------------------------------------------------------------------ + // Description: + // COMPARE_LITE_DATA(expected,actual) + // This task checks if the actual data is equal to the expected data. + // X is used as don't care but it is not permitted for the full vector + // to be don't care. + //------------------------------------------------------------------------ + `define S_AXI_DATA_BUS_WIDTH 32 + task automatic COMPARE_LITE_DATA; + input [`S_AXI_DATA_BUS_WIDTH-1:0]expected; + input [`S_AXI_DATA_BUS_WIDTH-1:0]actual; + begin + if (expected === 'hx || actual === 'hx) begin + $display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); + result_slave_lite = 0; + $stop; + end + + if (actual != expected) begin + $display("TESTBENCH ERROR! Data expected is not equal to actual.", + "\nexpected = 0x%h",expected, + "\nactual = 0x%h",actual); + result_slave_lite = 0; + $stop; + end + else + begin + $display("TESTBENCH Passed! Data expected is equal to actual.", + "\n expected = 0x%h",expected, + "\n actual = 0x%h",actual); + end + end + endtask + + task automatic S00_AXI_TEST; + begin + $display("---------------------------------------------------------"); + $display("EXAMPLE TEST : S00_AXI"); + $display("Simple register write and read example"); + $display("---------------------------------------------------------"); + + S00_AXI_mtestvectorlite = 0; + S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS; + S00_AXI_mtestProtection_lite = 0; + S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE; + + result_slave_lite = 1; + + for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1) + begin + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress, + S00_AXI_mtestProtection_lite, + S00_AXI_test_data_lite[S00_AXI_mtestvectorlite], + S00_AXI_mtestdatasizelite, + S00_AXI_lite_response); + $display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response); + CHECK_RESPONSE_OKAY(S00_AXI_lite_response); + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress, + S00_AXI_mtestProtection_lite, + S00_AXI_rd_data_lite, + S00_AXI_lite_response); + $display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response); + CHECK_RESPONSE_OKAY(S00_AXI_lite_response); + COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite); + $display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite); + S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004; + end + + $display("---------------------------------------------------------"); + $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); + if ( result_slave_lite ) begin + $display("PTGEN_TEST: PASSED!"); + end else begin + $display("PTGEN_TEST: FAILED!"); + end + $display("---------------------------------------------------------"); + end + endtask + + // Create the test vectors + initial begin + // When performing debug enable all levels of INFO messages. + wait(tb_ARESETn === 0) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1); + + // Create test data vectors + S00_AXI_test_data_lite[0] = 32'h0101FFFF; + S00_AXI_test_data_lite[1] = 32'habcd0001; + S00_AXI_test_data_lite[2] = 32'hdead0011; + S00_AXI_test_data_lite[3] = 32'hbeef0011; + end + + // Drive the BFM + initial begin + // Wait for end of reset + wait(tb_ARESETn === 0) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + + S00_AXI_TEST(); + + end + +endmodule diff --git a/system/ip/sja1000_1.0/example_designs/debug_hw_design/design.tcl b/system/ip/sja1000_1.0/example_designs/debug_hw_design/design.tcl new file mode 100644 index 0000000..52465f3 --- /dev/null +++ b/system/ip/sja1000_1.0/example_designs/debug_hw_design/design.tcl @@ -0,0 +1,175 @@ + +proc create_ipi_design { offsetfile design_name } { + + create_bd_design $design_name + open_bd_design $design_name + + # Create and configure Clock/Reset + create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0 + create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0 + + #check if current_board is set, if true - figure out required clocks. + set is_board_clock_found 0 + set is_board_reset_found 0 + set external_reset_port "" + set external_clock_port "" + + if { [current_board_part -quiet] != "" } { + + #check if any reset interface exists in board. + set board_reset [lindex [get_board_part_interfaces -filter { BUSDEF_NAME == reset_rtl && MODE == slave }] 0 ] + if { $board_reset ne "" } { + set is_board_reset_found 1 + apply_board_connection -board_interface $board_reset -ip_intf sys_clk_0/reset -diagram [current_bd_design] + apply_board_connection -board_interface $board_reset -ip_intf sys_reset_0/ext_reset -diagram [current_bd_design] + set external_rst [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/reset]]] + if { $external_rst ne "" } { + set external_reset_port [get_property NAME $external_rst] + } + } else { + send_msg "ptgen 51-200" WARNING "No reset interface found in current_board, Users may need to specify the location constraints manually." + } + + # check for differential clock, exclude any special clocks which has TYPE property. + set board_clock_busifs "" + foreach busif [get_board_part_interfaces -filter "BUSDEF_NAME == diff_clock_rtl"] { + set type [get_property PARAM.TYPE $busif] + if { $type == "" } { + set board_clock_busifs $busif + break + } + } + if { $board_clock_busifs ne "" } { + apply_board_connection -board_interface $board_clock_busifs -ip_intf sys_clk_0/CLK_IN1_D -diagram [current_bd_design] + set is_board_clock_found 1 + } else { + # check for single ended clock + set board_sclock_busifs [lindex [get_board_part_interfaces -filter "BUSDEF_NAME == clock_rtl"] 0 ] + if { $board_sclock_busifs ne "" } { + apply_board_connection -board_interface $board_sclock_busifs -ip_intf sys_clk_0/clock_CLK_IN1 -diagram [current_bd_design] + set external_clk [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/clk_in1]]] + if { $external_clk ne "" } { + set external_clock_port [get_property NAME $external_clk] + } + set is_board_clock_found 1 + } else { + send_msg "ptgen 51-200" WARNING "No clock interface found in current_board, Users may need to specify the location constraints manually." + } + } + + } else { + send_msg "ptgen 51-201" WARNING "No board selected in current_project. Users may need to specify the location constraints manually." + } + + #if there is no corresponding board interface found, assume constraints will be provided manually while pin planning. + if { $is_board_reset_found == 0 } { + create_bd_port -dir I -type rst reset_rtl + set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl] + connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl] + connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset] + set external_reset_port reset_rtl + } + if { $is_board_clock_found == 0 } { + create_bd_port -dir I -type clk clock_rtl + connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl] + set external_clock_port clock_rtl + } + + #Avoid IPI DRC, make clock port synchronous to reset + if { $external_clock_port ne "" && $external_reset_port ne "" } { + set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port] + } + + # Connect other sys_reset pins + connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked] + + # Create instance: sja1000_0, and set properties + set sja1000_0 [ create_bd_cell -type ip -vlnv user.org:user:sja1000:1.0 sja1000_0 ] + + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ] + set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0] + connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] + + # Create instance: axi_peri_interconnect, and set properties + set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ] + connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn] + set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect + connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] + connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI] + + set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect + connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] + + # Connect all clock & reset of sja1000_0 slave interfaces.. + connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins sja1000_0/S00_AXI] + connect_bd_net [get_bd_pins sja1000_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins sja1000_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] + + + # Auto assign address + assign_bd_address + + # Copy all address to sja1000_v1_0_include.tcl file + set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd + upvar 1 $offsetfile offset_file + set offset_file "${bd_path}/sja1000_v1_0_include.tcl" + set fp [open $offset_file "w"] + puts $fp "# Configuration address parameters" + + set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_sja1000_0_S00_AXI_* ]] + puts $fp "set s00_axi_addr ${offset}" + + close $fp +} + +# Set IP Repository and Update IP Catalogue +set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:sja1000:1.0]]]] +set hw_test_file ${ip_path}/example_designs/debug_hw_design/sja1000_v1_0_hw_test.tcl + +set repo_paths [get_property ip_repo_paths [current_fileset]] +if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { + set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] + update_ip_catalog +} + +set design_name "" +set all_bd {} +set all_bd_files [get_files *.bd -quiet] +foreach file $all_bd_files { +set file_name [string range $file [expr {[string last "/" $file] + 1}] end] +set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] +lappend all_bd $bd_name +} + +for { set i 1 } { 1 } { incr i } { + set design_name "sja1000_v1_0_hw_${i}" + if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { + break + } +} + +set intf_address_include_file "" +create_ipi_design intf_address_include_file ${design_name} +save_bd_design +validate_bd_design + +set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] +import_files -force -norecurse $wrapper_file + +puts "-------------------------------------------------------------------------------------------------" +puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, " +puts " please perform following steps to test design in targeted board." +puts "1. Generate bitstream" +puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target" +puts "3. Download generated bitstream" +puts "4. Run generated hardware test using below command, this invokes basic read/write operation" +puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0" +puts " : source -notrace ${hw_test_file}" +puts "-------------------------------------------------------------------------------------------------" + diff --git a/system/ip/sja1000_1.0/example_designs/debug_hw_design/sja1000_v1_0_hw_test.tcl b/system/ip/sja1000_1.0/example_designs/debug_hw_design/sja1000_v1_0_hw_test.tcl new file mode 100644 index 0000000..c67d298 --- /dev/null +++ b/system/ip/sja1000_1.0/example_designs/debug_hw_design/sja1000_v1_0_hw_test.tcl @@ -0,0 +1,45 @@ +# Runtime Tcl commands to interact with - sja1000_v1_0 + +# Sourcing design address info tcl +set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd +source ${bd_path}/sja1000_v1_0_include.tcl + +# jtag axi master interface hardware name, change as per your design. +set jtag_axi_master hw_axi_1 +set ec 0 + +# hw test script +# Delete all previous axis transactions +if { [llength [get_hw_axi_txns -quiet]] } { + delete_hw_axi_txn [get_hw_axi_txns -quiet] +} + + +# Test all lite slaves. +set wdata_1 abcd1234 + +# Test: S00_AXI +# Create a write transaction at s00_axi_addr address +create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1 +# Create a read transaction at s00_axi_addr address +create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr +# Initiate transactions +run_hw_axi r_s00_axi_addr +run_hw_axi w_s00_axi_addr +run_hw_axi r_s00_axi_addr +set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]] +# Compare read data +if { $rdata_tmp == $wdata_1 } { + puts "Data comparison test pass for - S00_AXI" +} else { + puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp" + inc ec +} + +# Check error flag +if { $ec == 0 } { + puts "PTGEN_TEST: PASSED!" +} else { + puts "PTGEN_TEST: FAILED!" +} + diff --git a/system/ip/sja1000_1.0/hdl/can_defines.v b/system/ip/sja1000_1.0/hdl/can_defines.v index e5c9843..f135781 100644 --- a/system/ip/sja1000_1.0/hdl/can_defines.v +++ b/system/ip/sja1000_1.0/hdl/can_defines.v @@ -106,7 +106,7 @@ // `define ALTERA_RAM // Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used) -`define XILINX_RAM +// `define XILINX_RAM // Uncomment the line for the ram used in ASIC implementation // `define VIRTUALSILICON_RAM diff --git a/system/ip/sja1000_1.0/hdl/can_ifc_axi.v b/system/ip/sja1000_1.0/hdl/can_ifc_axi.v index 3a498f9..e439536 100644 --- a/system/ip/sja1000_1.0/hdl/can_ifc_axi.v +++ b/system/ip/sja1000_1.0/hdl/can_ifc_axi.v @@ -86,90 +86,36 @@ module can_ifc_async end endmodule -module can_ifc_axi -#( - // Width of S_AXI data bus - parameter integer C_S_AXI_DATA_WIDTH = 32, - // Width of S_AXI address bus - parameter integer C_S_AXI_ADDR_WIDTH = 8 -) +module rw_arbiter #() ( - input wire clk_i, - output wire reg_rst_o, - output wire reg_cs_o, - output wire reg_we_o, - output wire [7:0] reg_addr_o, - output wire [7:0] reg_data_in_o, - input wire [7:0] reg_data_out_i, - input wire S_AXI_ACLK, input wire S_AXI_ARESETN, + output reg read_pending, + output reg read_active, + output reg write_pending, + output reg write_active, + output reg read_active_edge, + output reg write_active_edge, - input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR, - input wire [2:0] S_AXI_AWPROT, - input wire S_AXI_AWVALID, - output reg S_AXI_AWREADY, - - input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA, - input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB, - input wire S_AXI_WVALID, - output reg S_AXI_WREADY, - - output reg [1:0] S_AXI_BRESP, - output reg S_AXI_BVALID, - input wire S_AXI_BREADY, - - input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR, - input wire [2:0] S_AXI_ARPROT, - input wire S_AXI_ARVALID, - output reg S_AXI_ARREADY, - - output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA, // TODO: reg - output reg [1:0] S_AXI_RRESP, - output reg S_AXI_RVALID, - input wire S_AXI_RREADY + input wire read_finished, + input wire write_finished, + + input wire ready_read_i, + input wire ready_write_i ); -parameter Tp = 1; -/* -input clk_i; -output reg_rst_o; -output reg_cs_o; -output reg_we_o; -output [7:0] reg_data_in_o; -input [7:0] reg_data_out_i; -*/ + wire ready_read_edge; + wire ready_write_edge; + reg [1:0] ready_read_hist; + reg [1:0] ready_write_hist; + assign ready_read_edge = ready_read_hist[0] ^ ready_read_hist[1]; + assign ready_write_edge = ready_write_hist[0] ^ ready_write_hist[1]; - reg write_pending; - reg write_active; - reg read_pending; - reg read_active; - - reg [1:0] ready_read_hist; - reg [1:0] ready_write_hist; - wire ready_read_edge; - wire ready_write_edge; - assign ready_read_edge = ready_read_hist[0] ^ ready_read_hist[1]; - assign ready_write_edge = ready_write_hist[0] ^ ready_write_hist[1]; - - wire read_finished; - wire write_finished; - - reg read_active_edge; - reg write_active_edge; - - reg req; - reg oack; - wire ack_i; - - assign read_finished = S_AXI_RVALID; - assign write_finished = S_AXI_BVALID; - // read/write arbitration - always @ (posedge S_AXI_ACLK or negedge S_AXI_RST) + always @ (posedge S_AXI_ACLK or negedge S_AXI_ARESETN) begin - if (~S_AXI_RST) + if (~S_AXI_ARESETN) begin write_pending <= 1'b0; write_active <= 1'b0; @@ -180,8 +126,8 @@ input [7:0] reg_data_out_i; end else begin - ready_read_hist <= {ready_read_hist[0], S_AXI_ARVALID}; - ready_write_hist <= {ready_write_hist[0], S_AXI_AWVALID & S_AXI_WVALID /*& (S_AXI_WSTRB == 4'b1111)*/}; + ready_read_hist <= {ready_read_hist[0], ready_read_i}; + ready_write_hist <= {ready_write_hist[0], ready_write_i /*& (S_AXI_WSTRB == 4'b1111)*/}; /* if(S_AXI_AWVALID & S_AXI_WVALID & (S_AXI_WSTRB != 4'b1111)) @@ -241,6 +187,75 @@ input [7:0] reg_data_out_i; end end end +endmodule + +module can_ifc_axi +#( + // Width of S_AXI data bus + parameter integer C_S_AXI_DATA_WIDTH = 32, + // Width of S_AXI address bus + parameter integer C_S_AXI_ADDR_WIDTH = 8 +) +( + input wire clk_i, + output wire reg_rst_o, + output wire reg_cs_o, + output wire reg_we_o, + output wire [7:0] reg_addr_o, + output wire [7:0] reg_data_in_o, + input wire [7:0] reg_data_out_i, + + input wire S_AXI_ACLK, + input wire S_AXI_ARESETN, + + input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR, + input wire [2:0] S_AXI_AWPROT, + input wire S_AXI_AWVALID, + output reg S_AXI_AWREADY, + + input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA, + input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB, + input wire S_AXI_WVALID, + output reg S_AXI_WREADY, + + output reg [1:0] S_AXI_BRESP, + output reg S_AXI_BVALID, + input wire S_AXI_BREADY, + + input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR, + input wire [2:0] S_AXI_ARPROT, + input wire S_AXI_ARVALID, + output reg S_AXI_ARREADY, + + output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA, // TODO: reg + output reg [1:0] S_AXI_RRESP, + output reg S_AXI_RVALID, + input wire S_AXI_RREADY +); + + reg req; + reg oack; + wire ack_i; + wire read_active; + wire write_active; +rw_arbiter rw_arbiter_inst +( + .S_AXI_ACLK(S_AXI_ACLK), + .S_AXI_ARESETN(S_AXI_ARESETN), + .read_pending(), + .read_active(read_active), + .write_pending(), + .write_active(write_active), + .read_active_edge(read_active_edge), + .write_active_edge(write_active_edge), + + .read_finished(S_AXI_RVALID && S_AXI_RREADY), + .write_finished(S_AXI_BVALID && S_AXI_BREADY), + + .ready_read_i(S_AXI_ARVALID), + .ready_write_i(S_AXI_AWVALID & S_AXI_WVALID) +); + //assign reg_addr_o <= write ? axi_waddr : axi_raddr; // assign reg_addr_o - asynchronous, synchronized by protocols expectations @@ -258,16 +273,18 @@ input [7:0] reg_data_out_i; end */ - always @(negedge S_AXI_RST or posedge S_AXI_ACLK) + always @(negedge S_AXI_ARESETN or posedge S_AXI_ACLK) begin - if (~S_AXI_RST) + if (~S_AXI_ARESETN) begin + req <= 1'b0; oack <= 1'b0; //S_AXI_RDATA <=#C_S_AXI_DATA_WIDTH 0; - S_AXI_BRESP <= 0; + S_AXI_BRESP <= 2'b00; // OKAY S_AXI_BVALID <= 1'b0; S_AXI_WREADY <= 1'b0; S_AXI_AWREADY <= 1'b0; + S_AXI_RRESP <= 0; end else begin // no synchronization necessary @@ -278,34 +295,50 @@ input [7:0] reg_data_out_i; if (read_active) begin //S_AXI_RDATA <= reg_data_out_i; // TODO: should be allright, the address is stable ... - // read_active will be deasserted after asserting S_AXI_RVALID, so this will execute only 2x - S_AXI_RVALID <= ~S_AXI_RVALID; - S_AXI_ARREADY <= ~S_AXI_ARREADY; + if (S_AXI_RREADY && S_AXI_RVALID) + begin + S_AXI_RVALID <= 1'b0; + S_AXI_ARREADY <= 1'b0; + end + else if (~S_AXI_RVALID) + begin + S_AXI_RVALID <= 1'b1; + S_AXI_ARREADY <= 1'b1; + S_AXI_RRESP <= 2'b00; // OKAY + end end else if (write_active) begin - S_AXI_BRESP <= 2'b00; // TODO: value? - // write_active will be deasserted after asserting S_AXI_RVALID, so this will execute only 2x - S_AXI_BVALID <= ~S_AXI_BVALID; - S_AXI_WREADY <= ~S_AXI_WREADY; - S_AXI_AWREADY <= ~S_AXI_AWREADY; + if (S_AXI_BREADY && S_AXI_BVALID) + begin + S_AXI_BVALID <= 1'b0; + S_AXI_WREADY <= 1'b0; + S_AXI_AWREADY <= 1'b0; + end + else if (~S_AXI_BVALID) + begin + S_AXI_BRESP <= 2'b00; // OKAY + S_AXI_BVALID <= 1'b1; + S_AXI_WREADY <= 1'b1; + S_AXI_AWREADY <= 1'b1; + end end oack <= ~oack; end end end - assign reg_rst_o = ~S_AXI_RST; + assign reg_rst_o = ~S_AXI_ARESETN; assign reg_we_o = write_active; - assign reg_addr_o = S_AXI_AWADDR; // TODO: latch? - assign reg_data_in_o = S_AXI_WDATA; - assign S_AXI_RDATA = reg_data_out_i; // TODO: latch? + assign reg_data_in_o = S_AXI_WDATA[7:0]; + assign S_AXI_RDATA[7:0]= reg_data_out_i; // TODO: latch? + assign S_AXI_RDATA[C_S_AXI_DATA_WIDTH-1 : 8] = 0; can_ifc_async CAN_IFC_ASYNC ( .clk_i(clk_i), - .rstn_i(S_AXI_RST), + .rstn_i(S_AXI_ARESETN), .reg_cs_o(reg_cs_o), .req_i(req), - .ack_o(ack) + .ack_o(ack_i) ); endmodule diff --git a/system/ip/sja1000_1.0/hdl/sja1000.v b/system/ip/sja1000_1.0/hdl/sja1000.v index a613e88..64851fa 100644 --- a/system/ip/sja1000_1.0/hdl/sja1000.v +++ b/system/ip/sja1000_1.0/hdl/sja1000.v @@ -10,9 +10,10 @@ // Parameters of Axi Slave Bus Interface S00_AXI parameter integer C_S00_AXI_DATA_WIDTH = 32, - parameter integer C_S00_AXI_ADDR_WIDTH = 4, + parameter integer C_S00_AXI_ADDR_WIDTH = 8 // Parameters of Axi Slave Bus Interface S_AXI_INTR + /* parameter integer C_S_AXI_INTR_DATA_WIDTH = 32, parameter integer C_S_AXI_INTR_ADDR_WIDTH = 5, parameter integer C_NUM_OF_INTR = 1, @@ -20,13 +21,14 @@ parameter C_INTR_ACTIVE_STATE = 32'hFFFFFFFF, parameter integer C_IRQ_SENSITIVITY = 1, parameter integer C_IRQ_ACTIVE_STATE = 1 + */ ) ( // Users to add ports here input wire can_clk, input wire can_rx, output wire can_tx, - output wire bus_on_off, + output wire bus_off_on, // User ports ends // Do not modify the ports beyond this line @@ -55,6 +57,7 @@ input wire s00_axi_rready, // Ports of Axi Slave Bus Interface S_AXI_INTR + /* input wire s_axi_intr_aclk, input wire s_axi_intr_aresetn, input wire [C_S_AXI_INTR_ADDR_WIDTH-1 : 0] s_axi_intr_awaddr, @@ -76,8 +79,19 @@ output wire [1 : 0] s_axi_intr_rresp, output wire s_axi_intr_rvalid, input wire s_axi_intr_rready, + */ output wire irq ); + wire reg_we; + wire reg_cs; + wire reg_rst; + wire [7:0] reg_data_in; + wire [7:0] reg_data_out; + wire [7:0] reg_addr; + + wire irq_n; + assign irq = ~irq_n; + // Instantiation of Axi Bus Interface S00_AXI can_ifc_axi # ( .C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH), @@ -114,13 +128,6 @@ .reg_data_out_i(reg_data_out) ); - wire reg_we; - wire reg_cs; - wire reg_rst; - wire [7:0] reg_data_in; - wire [7:0] reg_data_out; - wire [7:0] reg_addr; - can_top_raw can_top_raw_inst ( .reg_we_i(reg_we), .reg_cs_i(reg_cs), @@ -133,7 +140,7 @@ .rx_i(can_rx), .tx_o(can_tx), .bus_off_on(bus_off_on), - .irq_on(irq), // TODO: test the compiler, this is multi-assigned output + .irq_on(irq_n), .clkout_o() ); diff --git a/system/ip/sja1000_1.0/xgui/sja1000_v1_0.tcl b/system/ip/sja1000_1.0/xgui/sja1000_v1_0.tcl index 255307c..d8bf174 100644 --- a/system/ip/sja1000_1.0/xgui/sja1000_v1_0.tcl +++ b/system/ip/sja1000_1.0/xgui/sja1000_v1_0.tcl @@ -3,22 +3,6 @@ proc init_gui { IPINST } { ipgui::add_param $IPINST -name "Component_Name" #Adding Page set Page_0 [ipgui::add_page $IPINST -name "Page 0"] - set C_S_AXI_INTR_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S_AXI_INTR_DATA_WIDTH" -parent ${Page_0} -widget comboBox] - set_property tooltip {Width of S_AXI data bus} ${C_S_AXI_INTR_DATA_WIDTH} - set C_S_AXI_INTR_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S_AXI_INTR_ADDR_WIDTH" -parent ${Page_0}] - set_property tooltip {Width of S_AXI address bus} ${C_S_AXI_INTR_ADDR_WIDTH} - set C_NUM_OF_INTR [ipgui::add_param $IPINST -name "C_NUM_OF_INTR" -parent ${Page_0}] - set_property tooltip {Number of Interrupts} ${C_NUM_OF_INTR} - set C_INTR_SENSITIVITY [ipgui::add_param $IPINST -name "C_INTR_SENSITIVITY" -parent ${Page_0}] - set_property tooltip {Each bit corresponds to Sensitivity of interrupt : 0 - EDGE, 1 - LEVEL} ${C_INTR_SENSITIVITY} - set C_INTR_ACTIVE_STATE [ipgui::add_param $IPINST -name "C_INTR_ACTIVE_STATE" -parent ${Page_0}] - set_property tooltip {Each bit corresponds to Sub-type of INTR: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_INTR_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_INTR_SENSITIVITY is LEVEL(1) ]} ${C_INTR_ACTIVE_STATE} - set C_IRQ_SENSITIVITY [ipgui::add_param $IPINST -name "C_IRQ_SENSITIVITY" -parent ${Page_0}] - set_property tooltip {Sensitivity of IRQ: 0 - EDGE, 1 - LEVEL} ${C_IRQ_SENSITIVITY} - set C_IRQ_ACTIVE_STATE [ipgui::add_param $IPINST -name "C_IRQ_ACTIVE_STATE" -parent ${Page_0}] - set_property tooltip {Sub-type of IRQ: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_IRQ_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_IRQ_SENSITIVITY is LEVEL(1) ]} ${C_IRQ_ACTIVE_STATE} - ipgui::add_param $IPINST -name "C_S_AXI_INTR_BASEADDR" -parent ${Page_0} - ipgui::add_param $IPINST -name "C_S_AXI_INTR_HIGHADDR" -parent ${Page_0} set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox] set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH} set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}] @@ -29,87 +13,6 @@ proc init_gui { IPINST } { } -proc update_PARAM_VALUE.C_S_AXI_INTR_DATA_WIDTH { PARAM_VALUE.C_S_AXI_INTR_DATA_WIDTH } { - # Procedure called to update C_S_AXI_INTR_DATA_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_S_AXI_INTR_DATA_WIDTH { PARAM_VALUE.C_S_AXI_INTR_DATA_WIDTH } { - # Procedure called to validate C_S_AXI_INTR_DATA_WIDTH - return true -} - -proc update_PARAM_VALUE.C_S_AXI_INTR_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_INTR_ADDR_WIDTH } { - # Procedure called to update C_S_AXI_INTR_ADDR_WIDTH when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_S_AXI_INTR_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_INTR_ADDR_WIDTH } { - # Procedure called to validate C_S_AXI_INTR_ADDR_WIDTH - return true -} - -proc update_PARAM_VALUE.C_NUM_OF_INTR { PARAM_VALUE.C_NUM_OF_INTR } { - # Procedure called to update C_NUM_OF_INTR when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_NUM_OF_INTR { PARAM_VALUE.C_NUM_OF_INTR } { - # Procedure called to validate C_NUM_OF_INTR - return true -} - -proc update_PARAM_VALUE.C_INTR_SENSITIVITY { PARAM_VALUE.C_INTR_SENSITIVITY } { - # Procedure called to update C_INTR_SENSITIVITY when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_INTR_SENSITIVITY { PARAM_VALUE.C_INTR_SENSITIVITY } { - # Procedure called to validate C_INTR_SENSITIVITY - return true -} - -proc update_PARAM_VALUE.C_INTR_ACTIVE_STATE { PARAM_VALUE.C_INTR_ACTIVE_STATE } { - # Procedure called to update C_INTR_ACTIVE_STATE when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_INTR_ACTIVE_STATE { PARAM_VALUE.C_INTR_ACTIVE_STATE } { - # Procedure called to validate C_INTR_ACTIVE_STATE - return true -} - -proc update_PARAM_VALUE.C_IRQ_SENSITIVITY { PARAM_VALUE.C_IRQ_SENSITIVITY } { - # Procedure called to update C_IRQ_SENSITIVITY when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_IRQ_SENSITIVITY { PARAM_VALUE.C_IRQ_SENSITIVITY } { - # Procedure called to validate C_IRQ_SENSITIVITY - return true -} - -proc update_PARAM_VALUE.C_IRQ_ACTIVE_STATE { PARAM_VALUE.C_IRQ_ACTIVE_STATE } { - # Procedure called to update C_IRQ_ACTIVE_STATE when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_IRQ_ACTIVE_STATE { PARAM_VALUE.C_IRQ_ACTIVE_STATE } { - # Procedure called to validate C_IRQ_ACTIVE_STATE - return true -} - -proc update_PARAM_VALUE.C_S_AXI_INTR_BASEADDR { PARAM_VALUE.C_S_AXI_INTR_BASEADDR } { - # Procedure called to update C_S_AXI_INTR_BASEADDR when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_S_AXI_INTR_BASEADDR { PARAM_VALUE.C_S_AXI_INTR_BASEADDR } { - # Procedure called to validate C_S_AXI_INTR_BASEADDR - return true -} - -proc update_PARAM_VALUE.C_S_AXI_INTR_HIGHADDR { PARAM_VALUE.C_S_AXI_INTR_HIGHADDR } { - # Procedure called to update C_S_AXI_INTR_HIGHADDR when any of the dependent parameters in the arguments change -} - -proc validate_PARAM_VALUE.C_S_AXI_INTR_HIGHADDR { PARAM_VALUE.C_S_AXI_INTR_HIGHADDR } { - # Procedure called to validate C_S_AXI_INTR_HIGHADDR - return true -} - proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { # Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change } @@ -147,41 +50,6 @@ proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } } -proc update_MODELPARAM_VALUE.C_S_AXI_INTR_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_INTR_DATA_WIDTH PARAM_VALUE.C_S_AXI_INTR_DATA_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C_S_AXI_INTR_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_INTR_DATA_WIDTH} -} - -proc update_MODELPARAM_VALUE.C_S_AXI_INTR_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_INTR_ADDR_WIDTH PARAM_VALUE.C_S_AXI_INTR_ADDR_WIDTH } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C_S_AXI_INTR_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_INTR_ADDR_WIDTH} -} - -proc update_MODELPARAM_VALUE.C_NUM_OF_INTR { MODELPARAM_VALUE.C_NUM_OF_INTR PARAM_VALUE.C_NUM_OF_INTR } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C_NUM_OF_INTR}] ${MODELPARAM_VALUE.C_NUM_OF_INTR} -} - -proc update_MODELPARAM_VALUE.C_INTR_SENSITIVITY { MODELPARAM_VALUE.C_INTR_SENSITIVITY PARAM_VALUE.C_INTR_SENSITIVITY } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C_INTR_SENSITIVITY}] ${MODELPARAM_VALUE.C_INTR_SENSITIVITY} -} - -proc update_MODELPARAM_VALUE.C_INTR_ACTIVE_STATE { MODELPARAM_VALUE.C_INTR_ACTIVE_STATE PARAM_VALUE.C_INTR_ACTIVE_STATE } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C_INTR_ACTIVE_STATE}] ${MODELPARAM_VALUE.C_INTR_ACTIVE_STATE} -} - -proc update_MODELPARAM_VALUE.C_IRQ_SENSITIVITY { MODELPARAM_VALUE.C_IRQ_SENSITIVITY PARAM_VALUE.C_IRQ_SENSITIVITY } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C_IRQ_SENSITIVITY}] ${MODELPARAM_VALUE.C_IRQ_SENSITIVITY} -} - -proc update_MODELPARAM_VALUE.C_IRQ_ACTIVE_STATE { MODELPARAM_VALUE.C_IRQ_ACTIVE_STATE PARAM_VALUE.C_IRQ_ACTIVE_STATE } { - # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value - set_property value [get_property value ${PARAM_VALUE.C_IRQ_ACTIVE_STATE}] ${MODELPARAM_VALUE.C_IRQ_ACTIVE_STATE} -} - proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} diff --git a/system/src/top/top.bd b/system/src/top/top.bd index d2df8a6..ddb7b7c 100644 --- a/system/src/top/top.bd +++ b/system/src/top/top.bd @@ -135,7 +135,96 @@ - + + + CAN1_TXD + + out + + + + CAN1_RXD + + in + + + + CAN2_TXD + + out + + + + CAN2_RXD + + in + + + + LED + + out + + 7 + 0 + + + + + KEY + + in + + 3 + 0 + + + + + SW + + in + + 7 + 0 + + + + + CAN_STBY + + out + + 0 + 0 + + + + + CAN3_TXD + + out + + + + CAN4_TXD + + out + + + + CAN3_RXD + + in + + + + CAN4_RXD + + in + + + @@ -173,7 +262,7 @@ 54.14 33.333333 667 - 200.000000 + 200 50 50 100 @@ -185,6 +274,7 @@ 0 0 0 + 1 1 1 0 @@ -194,6 +284,7 @@ 0 0 0 + 1 LVCMOS 3.3V LVCMOS 1.8V DDR 3 (Low Voltage) @@ -213,6 +304,7 @@ MIO 16 .. 27 1 MIO 52 .. 53 + 0 1 MIO 40 .. 45 1 @@ -223,6 +315,7 @@ MIO 48 .. 49 1 EMIO + 0 1 EMIO 1 @@ -232,7 +325,7 @@ 0 1 1 - 0 + 1 6:2:1 1000 Mbps ARM PLL @@ -357,7 +450,7 @@ top_processing_system7_0_axi_periph_0 - 1 + 2 xilinx.com:ip:axi_interconnect:2.1 @@ -369,10 +462,27 @@ - can_merge_0 - + xlconstant_0 + + + top_xlconstant_0_0 + 0 + + + + canbench_cc_gpio_0 + + + top_canbench_cc_gpio_0_0 + + + + sja1000_0 + - top_can_merge_0_0 + top_sja1000_0_0 + 0x43C00000 + 0x43C0FFFF @@ -382,6 +492,11 @@ + + processing_system7_0_axi_periph_M00_AXI + + + @@ -392,6 +507,9 @@ + + + processing_system7_0_FCLK_RESET0_N @@ -403,6 +521,8 @@ + + rst_processing_system7_0_100M_interconnect_aresetn @@ -410,20 +530,69 @@ - can_merge_0_can_rx - - - + canbench_cc_gpio_0_GPIO_I + + + + + processing_system7_0_GPIO_O + + + + + canbench_cc_gpio_0_LED + + + + + KEY_1 + + + + + SW_1 + + + + + xlconstant_0_dout + + + + + sja1000_0_can_tx + + processing_system7_0_CAN0_PHY_TX - + processing_system7_0_CAN1_PHY_TX - + + + + CAN1_RXD_1 + + + + + CAN2_RXD_1 + + + + + CAN3_RXD_1 + + + + + sja1000_0_irq + + @@ -454,6 +623,12 @@ + + M01_AXI + + + + CLK.ACLK Clk @@ -602,6 +777,62 @@ + + CLK.M01_ACLK + Clk + Clock + + + + + + + CLK + + + M01_ACLK + + + + + + ASSOCIATED_BUSIF + M01_AXI + + + + + + + + ASSOCIATED_RESET + M01_ARESETN + + + + + + + + + + RST.M01_ARESETN + Reset + Reset + + + + + + + RST + + + M01_ARESETN + + + + @@ -660,6 +891,22 @@ + + M01_ACLK + + in + + + + M01_ARESETN + + in + + 0 + 0 + + + @@ -670,22 +917,62 @@ processing_system7_0_axi_periph_imp 1.00.a + + xbar + + + top_xbar_0 + 1 + 2 + 0 + + s00_couplers + + m00_couplers + + + + m01_couplers + + - + + + s00_couplers_to_xbar + + + + + xbar_to_m00_couplers + + + + + xbar_to_m01_couplers + + + + processing_system7_0_axi_periph_ACLK_net - + + + + processing_system7_0_axi_periph_ARESETN_net - + + + + S00_ACLK_1 @@ -697,13 +984,36 @@ + + M00_ACLK_1 + + + + + M00_ARESETN_1 + + + + + M01_ACLK_1 + + + + + M01_ARESETN_1 + + + - - + + + + + @@ -711,7 +1021,7 @@ xilinx.com BlockDiagram/top_imp/processing_system7_0_axi_periph_imp - s00_couplers + m01_couplers 1.00.a @@ -844,7 +1154,7 @@ BlockDiagram :vivado.xilinx.com: - + @@ -887,13 +1197,418 @@ xilinx.com BlockDiagram/top_imp/processing_system7_0_axi_periph_imp - s00_couplers_imp + m01_couplers_imp 1.00.a - - + + + + + + + + xilinx.com + BlockDiagram/top_imp/processing_system7_0_axi_periph_imp + m00_couplers + 1.00.a + + + M_AXI + + + + + + S_AXI + + + + + + CLK.M_ACLK + Clk + Clock + + + + + + + CLK + + + M_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXI + + + + + + + + ASSOCIATED_RESET + M_ARESETN + + + + + + + + + + RST.M_ARESETN + Reset + Reset + + + + + + + RST + + + M_ARESETN + + + + + + CLK.S_ACLK + Clk + Clock + + + + + + + CLK + + + S_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI + + + + + + + + ASSOCIATED_RESET + S_ARESETN + + + + + + + + + + RST.S_ARESETN + Reset + Reset + + + + + + + RST + + + S_ARESETN + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + M_ACLK + + in + + + + M_ARESETN + + in + + 0 + 0 + + + + + S_ACLK + + in + + + + S_ARESETN + + in + + 0 + 0 + + + + + + + + + xilinx.com + BlockDiagram/top_imp/processing_system7_0_axi_periph_imp + m00_couplers_imp + 1.00.a + + + + + + + + + + + xilinx.com + BlockDiagram/top_imp/processing_system7_0_axi_periph_imp + s00_couplers + 1.00.a + + + M_AXI + + + + + + S_AXI + + + + + + CLK.M_ACLK + Clk + Clock + + + + + + + CLK + + + M_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXI + + + + + + + + ASSOCIATED_RESET + M_ARESETN + + + + + + + + + + RST.M_ARESETN + Reset + Reset + + + + + + + RST + + + M_ARESETN + + + + + + CLK.S_ACLK + Clk + Clock + + + + + + + CLK + + + S_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI + + + + + + + + ASSOCIATED_RESET + S_ARESETN + + + + + + + + + + RST.S_ARESETN + Reset + Reset + + + + + + + RST + + + S_ARESETN + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + M_ACLK + + in + + + + M_ARESETN + + in + + 0 + 0 + + + + + S_ACLK + + in + + + + S_ARESETN + + in + + 0 + 0 + + + + + + + + + xilinx.com + BlockDiagram/top_imp/processing_system7_0_axi_periph_imp + s00_couplers_imp + 1.00.a + + + auto_pc + + + top_auto_pc_0 + AXI3 + AXI4LITE + + + + + + + S_ACLK_1 + + + + + S_ARESETN_1 + + + + + + + + + + @@ -908,7 +1623,14 @@ Data 4G 32 - + + + SEG_sja1000_0_S00_AXI_reg + /sja1000_0/S00_AXI/S00_AXI_reg + 0x43C00000 + 64K + +