system: build fix, removed generated HDL wrappers

[fpga/zynq/canbench-sw.git] / system / script / recreate.tcl

diff --git a/system/script/recreate.tcl b/system/script/recreate.tcl
index f778e0538ad3e8c88e077a9915cf03ab9c344107..47e569297d039c97b16f6d0d3ca0befb56dc1bb3 100644 (file)
--- a/system/script/recreate.tcl
+++ b/system/script/recreate.tcl
@@ -1,38 +1,3 @@
-#
-# Vivado (TM) v2015.4 (64-bit)
-#
-# recreate.tcl: Tcl script for re-creating project 'canbench'
-#
-# Generated by Vivado on Fri Mar 25 10:03:14 CET 2016
-# IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
-#
-# This file contains the Vivado Tcl commands for re-creating the project to the state*
-# when this script was generated. In order to re-create the project, please source this
-# file in the Vivado Tcl Shell.
-#
-# * Note that the runs in the created project will be configured the same way as the
-#   original project, however they will not be launched automatically. To regenerate the
-#   run results please launch the synthesis/implementation runs as needed.
-#
-#*****************************************************************************************
-# NOTE: In order to use this script for source control purposes, please make sure that the
-#       following files are added to the source control system:-
-#
-# 1. This project restoration tcl script (recreate.tcl) that was generated.
-#
-# 2. The following source(s) files that were local or imported into the original project.
-#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
-#
-#    <none>
-#
-# 3. The following remote source files that were added to the original project:-
-#
-#    "/home/martin/projects/cvut/bakalarka/canbench-sw/system/src/top/top.bd"
-#    "/home/martin/projects/cvut/bakalarka/canbench-sw/system/src/top/hdl/top_wrapper.vhd"
-#    "/home/martin/projects/cvut/bakalarka/canbench-sw/system/project/canbench.srcs/constrs_1/new/top_wrapper.xdc"
-#
-#*****************************************************************************************
-
 # Set the reference directory for source file relative paths (by default the value is script directory path)
 set origin_dir "."
 
@@ -99,6 +64,7 @@ set_property "board_part" "em.avnet.com:microzed_7010:part0:1.0" $obj
 set_property "default_lib" "xil_defaultlib" $obj
 set_property "sim.ip.auto_export_scripts" "1" $obj
 set_property "simulator_language" "Mixed" $obj
+set_property "target_language" "VHDL" $obj
 
 # Create 'sources_1' fileset (if not found)
 if {[string equal [get_filesets -quiet sources_1] ""]} {
@@ -116,32 +82,19 @@ update_ip_catalog -rebuild
 set obj [get_filesets sources_1]
 set files [list \
  "[file normalize "$origin_dir/../src/top/top.bd"]"\
- "[file normalize "$origin_dir/../src/top/hdl/top_wrapper.vhd"]"\
 ]
 add_files -norecurse -fileset $obj $files
 
 # Set 'sources_1' fileset file properties for remote files
-set file "$origin_dir/../src/top/top.bd"
-set file [file normalize $file]
+# None
+
+# Set 'sources_1' fileset file properties for local files
+set file "top/top.bd"
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 if { ![get_property "is_locked" $file_obj] } {
-  set_property "generate_synth_checkpoint" "0" $file_obj
+  set_property "synth_checkpoint_mode" "Hierarchical" $file_obj
 }
 
-set file "$origin_dir/../src/top/hdl/top_wrapper.vhd"
-set file [file normalize $file]
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property "file_type" "VHDL" $file_obj
-
-
-# Set 'sources_1' fileset file properties for local files
-# None
-
-# Set 'sources_1' fileset properties
-set obj [get_filesets sources_1]
-set_property "top" "top_wrapper" $obj
-set_property elab_link_dcps false $obj
-
 # Create 'constrs_1' fileset (if not found)
 if {[string equal [get_filesets -quiet constrs_1] ""]} {
   create_fileset -constrset constrs_1
@@ -149,10 +102,10 @@ if {[string equal [get_filesets -quiet constrs_1] ""]} {
 
 # Set 'constrs_1' fileset object
 set obj [get_filesets constrs_1]
-
-# Add/Import constrs file and set constrs file properties
+# Empty (no sources present)
 
 # Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
 
 # Create 'sim_1' fileset (if not found)
 if {[string equal [get_filesets -quiet sim_1] ""]} {
@@ -165,7 +118,6 @@ set obj [get_filesets sim_1]
 
 # Set 'sim_1' fileset properties
 set obj [get_filesets sim_1]
-set_property "top" "top_wrapper" $obj
 set_property "xelab.nosort" "1" $obj
 set_property "xelab.unifast" "" $obj
 
@@ -177,6 +129,7 @@ if {[string equal [get_runs -quiet synth_1] ""]} {
   set_property flow "Vivado Synthesis 2015" [get_runs synth_1]
 }
 set obj [get_runs synth_1]
+set_property "needs_refresh" "1" $obj
 
 # set the current synth run
 current_run -synthesis [get_runs synth_1]
@@ -188,11 +141,23 @@ if {[string equal [get_runs -quiet impl_1] ""]} {
   set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
   set_property flow "Vivado Implementation 2015" [get_runs impl_1]
 }
+
+# Create block design
+#source ../src/top/top.tcl
+
+# Generate the wrapper
+open_bd_design ../src/top/top.bd
+set design_name [get_bd_designs]
+set obj [get_files $design_name.bd]
+make_wrapper -files $obj -top -import
+
+# set the current impl run
 set obj [get_runs impl_1]
+set_property "needs_refresh" "1" $obj
 set_property "steps.write_bitstream.args.readback_file" "0" $obj
 set_property "steps.write_bitstream.args.verbose" "0" $obj
-
-# set the current impl run
 current_run -implementation [get_runs impl_1]
 
+
+
 puts "INFO: Project created:canbench"