xilinx.com BlockDiagram top 1.00.a isTop true DDR TIMEPERIOD_PS 1250 MEMORY_TYPE COMPONENTS DATA_WIDTH 8 CS_ENABLED true DATA_MASK_ENABLED true SLOT Single MEM_ADDR_MAP ROW_COLUMN_BANK BURST_LENGTH 8 AXI_ARBITRATION_SCHEME TDM CAS_LATENCY 11 CAS_WRITE_LATENCY 11 FIXED_IO BlockDiagram :vivado.xilinx.com: CAN1_TXD out CAN1_RXD in CAN2_TXD out CAN2_RXD in LED out 7 0 KEY in 3 0 SW in 7 0 CAN_STBY out 0 0 CAN3_TXD out CAN4_TXD out CAN3_RXD in CAN4_RXD in xilinx.com BlockDiagram top_imp 1.00.a processing_system7_0 top_processing_system7_0_0 true -0.073 -0.072 0.024 0.023 0.294 0.298 0.338 0.334 50.05 50.43 50.10 50.01 49.59 51.74 50.32 48.55 39.7 39.7 54.14 54.14 33.333333 667 200 50 50 100 100 33.333333 50 533.333374 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1 LVCMOS 3.3V LVCMOS 1.8V DDR 3 (Low Voltage) 32 Bit 8 MT41K256M16 RE-125 1 1 1 1 1 1 MIO 1 .. 6 1 MIO 8 1 MIO 16 .. 27 1 MIO 52 .. 53 0 1 MIO 40 .. 45 1 MIO 46 1 MIO 50 1 MIO 48 .. 49 1 EMIO 0 1 EMIO 1 EMIO 1 MIO 28 .. 39 0 1 1 1 6:2:1 1000 Mbps ARM PLL DDR PLL IO PLL IO PLL IO PLL IO PLL IO PLL IO PLL IO PLL IO PLL CPU_1X CPU_1X CPU_1X disabled slow disabled slow slow slow slow slow slow slow slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow disabled slow clg400 processing_system7_0_axi_periph top_processing_system7_0_axi_periph_0 2 xilinx.com:ip:axi_interconnect:2.1 rst_processing_system7_0_100M top_rst_processing_system7_0_100M_0 xlconstant_0 top_xlconstant_0_0 0 canbench_cc_gpio_0 top_canbench_cc_gpio_0_0 sja1000_0 top_sja1000_0_0 0x43C00000 0x43C0FFFF processing_system7_0_M_AXI_GP0 processing_system7_0_axi_periph_M00_AXI processing_system7_0_FCLK_CLK0 processing_system7_0_FCLK_RESET0_N rst_processing_system7_0_100M_peripheral_aresetn rst_processing_system7_0_100M_interconnect_aresetn canbench_cc_gpio_0_GPIO_I processing_system7_0_GPIO_O canbench_cc_gpio_0_LED KEY_1 SW_1 xlconstant_0_dout sja1000_0_can_tx processing_system7_0_CAN0_PHY_TX processing_system7_0_CAN1_PHY_TX CAN1_RXD_1 CAN2_RXD_1 CAN3_RXD_1 sja1000_0_irq xilinx.com BlockDiagram/top_imp processing_system7_0_axi_periph 1.00.a S00_AXI M00_AXI M01_AXI CLK.ACLK Clk Clock CLK ACLK RST.ARESETN Reset Reset RST ARESETN CLK.S00_ACLK Clk Clock CLK S00_ACLK ASSOCIATED_BUSIF S00_AXI ASSOCIATED_RESET S00_ARESETN RST.S00_ARESETN Reset Reset RST S00_ARESETN CLK.M00_ACLK Clk Clock CLK M00_ACLK ASSOCIATED_BUSIF M00_AXI ASSOCIATED_RESET M00_ARESETN RST.M00_ARESETN Reset Reset RST M00_ARESETN CLK.M01_ACLK Clk Clock CLK M01_ACLK ASSOCIATED_BUSIF M01_AXI ASSOCIATED_RESET M01_ARESETN RST.M01_ARESETN Reset Reset RST M01_ARESETN BlockDiagram :vivado.xilinx.com: ACLK in ARESETN in 0 0 S00_ACLK in S00_ARESETN in 0 0 M00_ACLK in M00_ARESETN in 0 0 M01_ACLK in M01_ARESETN in 0 0 xilinx.com BlockDiagram/top_imp processing_system7_0_axi_periph_imp 1.00.a xbar top_xbar_0 1 2 0 s00_couplers m00_couplers m01_couplers s00_couplers_to_xbar xbar_to_m00_couplers xbar_to_m01_couplers processing_system7_0_axi_periph_ACLK_net processing_system7_0_axi_periph_ARESETN_net S00_ACLK_1 S00_ARESETN_1 M00_ACLK_1 M00_ARESETN_1 M01_ACLK_1 M01_ARESETN_1 xilinx.com BlockDiagram/top_imp/processing_system7_0_axi_periph_imp m01_couplers 1.00.a M_AXI S_AXI CLK.M_ACLK Clk Clock CLK M_ACLK ASSOCIATED_BUSIF M_AXI ASSOCIATED_RESET M_ARESETN RST.M_ARESETN Reset Reset RST M_ARESETN CLK.S_ACLK Clk Clock CLK S_ACLK ASSOCIATED_BUSIF S_AXI ASSOCIATED_RESET S_ARESETN RST.S_ARESETN Reset Reset RST S_ARESETN BlockDiagram :vivado.xilinx.com: M_ACLK in M_ARESETN in 0 0 S_ACLK in S_ARESETN in 0 0 xilinx.com BlockDiagram/top_imp/processing_system7_0_axi_periph_imp m01_couplers_imp 1.00.a xilinx.com BlockDiagram/top_imp/processing_system7_0_axi_periph_imp m00_couplers 1.00.a M_AXI S_AXI CLK.M_ACLK Clk Clock CLK M_ACLK ASSOCIATED_BUSIF M_AXI ASSOCIATED_RESET M_ARESETN RST.M_ARESETN Reset Reset RST M_ARESETN CLK.S_ACLK Clk Clock CLK S_ACLK ASSOCIATED_BUSIF S_AXI ASSOCIATED_RESET S_ARESETN RST.S_ARESETN Reset Reset RST S_ARESETN BlockDiagram :vivado.xilinx.com: M_ACLK in M_ARESETN in 0 0 S_ACLK in S_ARESETN in 0 0 xilinx.com BlockDiagram/top_imp/processing_system7_0_axi_periph_imp m00_couplers_imp 1.00.a xilinx.com BlockDiagram/top_imp/processing_system7_0_axi_periph_imp s00_couplers 1.00.a M_AXI S_AXI CLK.M_ACLK Clk Clock CLK M_ACLK ASSOCIATED_BUSIF M_AXI ASSOCIATED_RESET M_ARESETN RST.M_ARESETN Reset Reset RST M_ARESETN CLK.S_ACLK Clk Clock CLK S_ACLK ASSOCIATED_BUSIF S_AXI ASSOCIATED_RESET S_ARESETN RST.S_ARESETN Reset Reset RST S_ARESETN BlockDiagram :vivado.xilinx.com: M_ACLK in M_ARESETN in 0 0 S_ACLK in S_ARESETN in 0 0 xilinx.com BlockDiagram/top_imp/processing_system7_0_axi_periph_imp s00_couplers_imp 1.00.a auto_pc top_auto_pc_0 AXI3 AXI4LITE S_ACLK_1 S_ARESETN_1 xilinx.com Addressing/processing_system7_0 processing_system7 5.5 Data 4G 32 SEG_sja1000_0_S00_AXI_reg /sja1000_0/S00_AXI/S00_AXI_reg 0x43C00000 64K