]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-hw.git/commit
layout: main regulator
authorMartin Jerabek <jerabma7@fel.cvut.cz>
Wed, 13 Apr 2016 21:22:46 +0000 (23:22 +0200)
committerMartin Jerabek <jerabma7@fel.cvut.cz>
Wed, 13 Apr 2016 21:25:06 +0000 (23:25 +0200)
commita46d4e8446b05cc625efbd15ddf55461c187b3c8
tree323640f4a1c3fc006998695be13296010b7cfcb5
parent8a1cbee691141a98459392a13770a855ca3b447c
layout: main regulator
canbench-hw.kicad_pcb