X-Git-Url: http://rtime.felk.cvut.cz/gitweb/fpga/zynq/canbench-hw.git/blobdiff_plain/a46d4e8446b05cc625efbd15ddf55461c187b3c8..9128859699c7b638e2431fdb06686ae66eb30087:/jx2.sch diff --git a/jx2.sch b/jx2.sch index 97cd308..8fade49 100644 --- a/jx2.sch +++ b/jx2.sch @@ -150,30 +150,30 @@ $EndComp $Comp L VCCIO_35 #PWR083 U 1 1 5713CFBF -P 10000 4800 -F 0 "#PWR083" H 10000 4650 50 0001 C CNN -F 1 "VCCIO_35" H 10000 4950 50 0000 C CNN -F 2 "" H 10000 4800 50 0000 C CNN -F 3 "" H 10000 4800 50 0000 C CNN - 1 10000 4800 +P 10650 4800 +F 0 "#PWR083" H 10650 4650 50 0001 C CNN +F 1 "VCCIO_35" H 10650 4950 50 0000 C CNN +F 2 "" H 10650 4800 50 0000 C CNN +F 3 "" H 10650 4800 50 0000 C CNN + 1 10650 4800 1 0 0 -1 $EndComp -Text Label 6700 5000 0 60 ~ 0 -CAN1_RXD -Text Label 6700 5100 0 60 ~ 0 +Text Label 10400 4300 2 60 ~ 0 CAN1_TXD -Text Label 6700 4600 0 60 ~ 0 -CAN2_RXD -Text Label 6700 4700 0 60 ~ 0 +Text Label 10400 4400 2 60 ~ 0 +CAN1_RXD +Text Label 10400 4600 2 60 ~ 0 CAN2_TXD -Text Label 6700 4300 0 60 ~ 0 -CAN3_RXD -Text Label 6700 4400 0 60 ~ 0 +Text Label 10400 4700 2 60 ~ 0 +CAN2_RXD +Text Label 10400 5000 2 60 ~ 0 CAN3_TXD -Text Label 6700 4000 0 60 ~ 0 -CAN4_RXD -Text Label 6700 4100 0 60 ~ 0 +Text Label 10400 5100 2 60 ~ 0 +CAN3_RXD +Text Label 10400 5300 2 60 ~ 0 CAN4_TXD +Text Label 10400 5400 2 60 ~ 0 +CAN4_RXD $Comp L VCCIO_35 #PWR084 U 1 1 5713CFCD @@ -378,25 +378,25 @@ Wire Wire Line 7400 4800 7400 4900 Connection ~ 7400 4900 Wire Wire Line - 9550 4900 10000 4900 + 9550 4900 10650 4900 Wire Wire Line - 10000 4900 10000 4800 + 10650 4900 10650 4800 Wire Wire Line - 6700 5000 7550 5000 + 10400 4300 9550 4300 Wire Wire Line - 6700 5100 7550 5100 + 10400 4400 9550 4400 Wire Wire Line - 6700 4600 7550 4600 + 10400 4600 9550 4600 Wire Wire Line - 6700 4700 7550 4700 + 10400 4700 9550 4700 Wire Wire Line - 6700 4300 7550 4300 + 10400 5000 9550 5000 Wire Wire Line - 6700 4400 7550 4400 + 10400 5100 9550 5100 Wire Wire Line - 6700 4000 7550 4000 + 10400 5300 9550 5300 Wire Wire Line - 6700 4100 7550 4100 + 10400 5400 9550 5400 Wire Wire Line 1150 1350 1150 1450 Wire Wire Line @@ -480,13 +480,13 @@ Wire Wire Line Wire Wire Line 9550 3700 10450 3700 Wire Wire Line - 9550 4300 10450 4300 + 7550 5000 6650 5000 Wire Wire Line - 9550 4400 10450 4400 + 7550 5100 6650 5100 Wire Wire Line - 9550 4700 10450 4700 + 7550 5400 6650 5400 Wire Wire Line - 9550 4600 10450 4600 + 7550 5300 6650 5300 Wire Wire Line 9550 4100 10450 4100 Wire Wire Line @@ -529,13 +529,13 @@ Text Label 10450 4000 2 60 ~ 0 SW3 Text Label 10450 4100 2 60 ~ 0 SW4 -Text Label 10450 4300 2 60 ~ 0 +Text Label 6650 5000 0 60 ~ 0 SW5 -Text Label 10450 4400 2 60 ~ 0 +Text Label 6650 5100 0 60 ~ 0 SW6 -Text Label 10450 4600 2 60 ~ 0 +Text Label 6650 5300 0 60 ~ 0 SW7 -Text Label 10450 4700 2 60 ~ 0 +Text Label 6650 5400 0 60 ~ 0 SW8 NoConn ~ 9550 5600 NoConn ~ 9550 5800 @@ -720,16 +720,9 @@ NoConn ~ 7550 3300 NoConn ~ 7550 3400 NoConn ~ 7550 3600 NoConn ~ 7550 3700 -NoConn ~ 7550 5300 -NoConn ~ 7550 5400 NoConn ~ 7550 5600 NoConn ~ 7550 5700 -NoConn ~ 7550 5800 NoConn ~ 7550 5900 -NoConn ~ 9550 5400 -NoConn ~ 9550 5300 -NoConn ~ 9550 5100 -NoConn ~ 9550 5000 NoConn ~ 9550 1600 $Comp L VCCIO_35 #PWR088 @@ -757,4 +750,27 @@ Wire Wire Line 7550 1600 6450 1600 Text Label 6450 1600 0 60 ~ 0 CAN_STBY +$Comp +L VCCIO_35 #PWR090 +U 1 1 57103C6E +P 6450 5700 +F 0 "#PWR090" H 6450 5550 50 0001 C CNN +F 1 "VCCIO_35" H 6450 5850 50 0000 C CNN +F 2 "" H 6450 5700 50 0000 C CNN +F 3 "" H 6450 5700 50 0000 C CNN + 1 6450 5700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6450 5800 7550 5800 +Wire Wire Line + 6450 5800 6450 5700 +Text Notes 6050 6300 0 60 ~ 0 +JX2.98 is for\nVCCIO_13, assign\nsame voltage as \nVCCIO_35 +NoConn ~ 7550 4000 +NoConn ~ 7550 4100 +NoConn ~ 7550 4300 +NoConn ~ 7550 4400 +NoConn ~ 7550 4600 +NoConn ~ 7550 4700 $EndSCHEMATC