layout: finished routing

[fpga/zynq/canbench-hw.git] / can.sch

diff --git a/can.sch b/can.sch
index 8b28fc463b326abec190028c9cc9f7739adf7dba..fa9a8d2282f758375e4bf6b571abd625dabf62bd 100644 (file)
--- a/can.sch
+++ b/can.sch
@@ -77,6 +77,7 @@ LIBS:mcp
 LIBS:JX1
 LIBS:JX2
 LIBS:gates
+LIBS:usblc6
 LIBS:canbench-hw-cache
 EELAYER 25 0
 EELAYER END
@@ -281,7 +282,7 @@ U 1 1 570CC4EE
 P 4850 1300
 F 0 "JP3" H 4850 1380 50  0000 C CNN
 F 1 "Jumper_NC_Small" H 4860 1240 50  0001 C CNN
-F 2 "Pin_Headers:Pin_Header_Straight_1x02" H 4850 1300 50  0001 C CNN
+F 2 "footprints:Pin_Header_Straight_1x02" H 4850 1300 50  0001 C CNN
 F 3 "" H 4850 1300 50  0000 C CNN
        1    4850 1300
        -1   0    0    -1  
@@ -292,7 +293,7 @@ U 1 1 570CC765
 P 4850 1050
 F 0 "JP2" H 4850 1130 50  0000 C CNN
 F 1 "Jumper_NC_Small" H 4860 990 50  0001 C CNN
-F 2 "Pin_Headers:Pin_Header_Straight_1x02" H 4850 1050 50  0001 C CNN
+F 2 "footprints:Pin_Header_Straight_1x02" H 4850 1050 50  0001 C CNN
 F 3 "" H 4850 1050 50  0000 C CNN
        1    4850 1050
        -1   0    0    -1