power reg changed, I/O pin assignment, testpoints, CAN

[fpga/zynq/canbench-hw.git] / can.sch

diff --git a/can.sch b/can.sch
index 66b800a2bf99b1b107d34fa6c318916fdef2cd0a..eccfd18268a3d182e3069880a502674fa2ada84a 100644 (file)
--- a/can.sch
+++ b/can.sch
@@ -74,15 +74,15 @@ LIBS:Zilog
 LIBS:conn_100pin
 LIBS:MCP2562FD
 LIBS:vccio
+LIBS:mcp
 LIBS:JX1
 LIBS:JX2
-LIBS:mcp
 LIBS:canbench-hw-cache
 EELAYER 25 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
-Sheet 5 10
+Sheet 4 10
 Title ""
 Date ""
 Rev ""
@@ -296,4 +296,23 @@ Text Label 4250 1050 0    60   ~ 0
 COM_LO
 Text Notes 4250 850  0    60   ~ 0
 Common CANbus termination
+$Comp
+L R R52
+U 1 1 5707BAE6
+P 4750 1300
+F 0 "R52" V 4830 1300 50  0000 C CNN
+F 1 "120R" V 4750 1300 50  0000 C CNN
+F 2 "Resistors_SMD:R_0805_HandSoldering" V 4680 1300 50  0001 C CNN
+F 3 "" H 4750 1300 50  0000 C CNN
+       1    4750 1300
+       0    1    1    0   
+$EndComp
+Wire Wire Line
+       4600 1300 4250 1300
+Wire Wire Line
+       4900 1300 5250 1300
+Text Label 5250 1300 2    60   ~ 0
+COM_HI
+Text Label 4250 1300 0    60   ~ 0
+COM_LO
 $EndSCHEMATC