From: Vladimir Burian Date: Sun, 9 Jan 2011 12:25:52 +0000 (+0100) Subject: Copied all needed files. X-Git-Url: http://rtime.felk.cvut.cz/gitweb/fpga/virtex2/uart.git/commitdiff_plain/a24f1edd0b700eb64b3e56835af9a69f926ac0d6 Copied all needed files. --- diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..80fbf43 --- /dev/null +++ b/Makefile @@ -0,0 +1,142 @@ +# TOP - Name of the top-level module +# DEVICE - Name of the FPGA device (device-package-speed) +# PRJ - Name of .prj file with names of all source files. See XST manual. +# BMM - If design contains initialized memories, softcore MCU, etc., this +# file describes mapping of .elf file to these memories. Only one +# .bmm file can be used. +# ELF - File containing initialization data of memories described by +# previously defined .bmm file. Format can be .elf or .mem. +# SEARCH_DIRS - Directories to search when searching for netlists (.ngc, ...). +# See NGDBUILD manual. +# JTAG_POS - Position of device in JTAG chain. Used when downloading bit stream. +# INTSTYLE - Style of screen output. (ise | xflow | silent) + + +TOP = openMSP430_uart +DEVICE = xc2v1000-fg456 + +PRJ = openMSP430_uart.prj + +BMM = memory.bmm +ELF = software/ta_uart.elf + +SEARCH_DIRS = coregen + +JTAG_POS = 2 +INTSTYLE = xflow + + +ifneq (${strip ${BMM}},) + BITFILE = ${TOP}_rp.bit +else + BITFILE = ${TOP}.bit +endif + +#=============================================================================== + +.PHONY: all synth ngdbuild map implement download clean + +all: clean implement + +implement: ${BITFILE} + +#=============================================================================== + +synth ${TOP}.ngc: ${PRJ} + echo " \ + run \ + ${addprefix -ifn ,${PRJ}} \ + -ifmt mixed \ + -ofn ${TOP}.ngc \ + -ofmt NGC \ + -top ${TOP} \ + -p ${DEVICE} \ + -opt_mode Speed \ + -opt_level 1" \ + | xst + + +ngdbuild ${TOP}.ngd: ${TOP}.ngc ${BMM} ${TOP}.ucf + ngdbuild \ + ${addprefix -bm ,${BMM}} \ + -intstyle ${INTSTYLE} \ + -p ${DEVICE} \ + -uc ${TOP}.ucf \ + ${addprefix -sd ,${SEARCH_DIRS}} \ + ${TOP}.ngc \ + ${TOP}.ngd + + +map ${TOP}.ncd: ${TOP}.ngd + map \ + -p ${DEVICE} \ + -intstyle ${INTSTYLE} \ + ${TOP}.ngd \ + ${TOP}.pcf + par \ + -w ${TOP}.ncd \ + -intstyle ${INTSTYLE} \ + ${TOP}.ncd \ + ${TOP}.pcf + + +${TOP}.bit: ${TOP}.ncd + bitgen -w ${TOP}.ncd ${TOP}.bit ${TOP}.pcf + +${TOP}_rp.bit: ${TOP}.bit ${ELF} + data2mem -bm ${basename ${BMM}}_bd.bmm -bd ${ELF} -bt ${TOP}.bit -o b ${TOP}_rp.bit + +download: ${BITFILE} + /bin/echo -e "\ + setMode -bscan \n\ + cleancablelock \n\ + setCable -port auto \n\ + identify \n\ + assignFile -p ${JTAG_POS} -file ${BITFILE} \n\ + program -p ${JTAG_POS} \n\ + exit" | impact -batch + +#=============================================================================== + +clean: + rm -f _impactbatch.log + rm -f ${basename ${BMM}}_bd.bmm + rm -f netlist.lst + rm -f ${TOP}.bgn + rm -f ${TOP}.bit + rm -f ${TOP}.bld + rm -f ${TOP}.d + rm -f ${TOP}.drc + rm -f ${TOP}.lso + rm -f ${TOP}.map + rm -f ${TOP}.mrp + rm -f ${TOP}.ncd + rm -f ${TOP}.ngc + rm -f ${TOP}.ngd + rm -f ${TOP}.ngm + rm -f ${TOP}.pad + rm -f ${TOP}_pad.csv + rm -f ${TOP}_pad.txt + rm -f ${TOP}.par + rm -f ${TOP}.pcf + rm -f ${TOP}_rp.bit + rm -f ${TOP}_summary.xml + rm -f ${TOP}.unroutes + rm -f ${TOP}_usage.xml + rm -f ${TOP}.xpi + rm -rf xst + +#=============================================================================== + +%.d: %.prj + sed -e 's/#.*//' \ + -e 's/[ \t][ \t]*/ /g' \ + -e 's/^ //' -e 's/ $$//' \ + -e 's|\(.*\) \(.*\) \(.*\)|$<: \3|' \ + <$< >$@ + +%.prj: + touch $@ + +include ${PRJ:.prj=.d} + diff --git a/coregen/coregen.cgp b/coregen/coregen.cgp new file mode 100644 index 0000000..010dcf3 --- /dev/null +++ b/coregen/coregen.cgp @@ -0,0 +1,20 @@ +# Date: Sat Jan 8 21:37:24 2011 +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc2v1000 +SET devicefamily = virtex2 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -6 +SET verilogsim = False +SET vhdlsim = True +SET workingdirectory = /home/vladimir/xilinx/leds_v/coregen/tmp/ + diff --git a/coregen/ram_8x512.asy b/coregen/ram_8x512.asy new file mode 100644 index 0000000..1d168d3 --- /dev/null +++ b/coregen/ram_8x512.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 32 0 320 272 +PIN 0 48 LEFT 36 +PINATTR PinName addr[8:0] +PINATTR Polarity IN +LINE Wide 0 48 32 48 +PIN 0 80 LEFT 36 +PINATTR PinName din[7:0] +PINATTR Polarity IN +LINE Wide 0 80 32 80 +PIN 0 112 LEFT 36 +PINATTR PinName we +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 144 LEFT 36 +PINATTR PinName en +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 240 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 352 48 RIGHT 36 +PINATTR PinName dout[7:0] +PINATTR Polarity OUT +LINE Wide 320 48 352 48 diff --git a/coregen/ram_8x512.ngc b/coregen/ram_8x512.ngc new file mode 100644 index 0000000..3f79b5d --- /dev/null +++ b/coregen/ram_8x512.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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d>=0<1vi850;0xZfc<5891=n5+a98;2>{tl<0;6?uQce9>56<6j2.j4768;|qg0?6=:rTho63>3;3b?!g?2120q~kk:181[c334;86?o4$`:9"f032h7p}j9;296~Xb927:?7<8;%c;>=b7}Yll16=>4=4:&b52z\g`>;6;3887)o7:838yvca2909wSki;<37>7`<,h215?5rsg094?4|Vo801<;52g9'e=<><2wx5:4?:3y>51<>m27:?7de?7>51zJb=>{i==0;65<6sAk27p`:7;295~Nf12we954?:0yKe<=zf<31<7?tH`;8yk3f290:wEo6;|l6f?6=9rBj56sa5b83>4}Oi01vb8j50;3xLd?{Ic:?xh2n3:1=vFn9:m25<728qCm45rn7394?7|@h30qc8=:182Mg>3td=?7>51zJb=>{i>=0;65<6sAk27p`97;295~Nf12we:54?:0yKe<=zf?31<7?tH`;8yk0f290:wEo6;|l5f?6=9rBj56sa6b83>4}Oi01vb;j50;3xLd?{Ic:?xh1n3:1=vFn9:m35<728qCm45rn6394?7|@h30qpsr@AAx=4 "0", + c_has_en => 1, + c_reg_inputs => 0, + c_yclk_is_rising => 1, + c_ysinit_is_high => 1, + c_ywe_is_high => 0, + c_yprimitive_type => "16kx1", + c_ytop_addr => "1024", + c_yhierarchy => "hierarchy1", + c_has_limit_data_pitch => 0, + c_has_rdy => 0, + c_write_mode => 0, + c_width => 8, + c_yuse_single_primitive => 0, + c_has_nd => 0, + c_has_we => 1, + c_enable_rlocs => 0, + c_has_rfd => 0, + c_has_din => 1, + c_ybottom_addr => "0", + c_pipe_stages => 0, + c_yen_is_high => 0, + c_depth => 512, + c_has_default_data => 1, + c_limit_data_pitch => 18, + c_has_sinit => 0, + c_yydisable_warnings => 1, + c_mem_init_file => "mif_file_16_1", + c_default_data => "0", + c_ymake_bmm => 0, + c_addr_width => 9); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_ram_8x512 + port map ( + addr => addr, + clk => clk, + din => din, + dout => dout, + en => en, + we => we); +-- synthesis translate_on + +END ram_8x512_a; + diff --git a/coregen/ram_8x512.vho b/coregen/ram_8x512.vho new file mode 100644 index 0000000..1c9cc4b --- /dev/null +++ b/coregen/ram_8x512.vho @@ -0,0 +1,66 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component ram_8x512 + port ( + addr: IN std_logic_VECTOR(8 downto 0); + clk: IN std_logic; + din: IN std_logic_VECTOR(7 downto 0); + dout: OUT std_logic_VECTOR(7 downto 0); + en: IN std_logic; + we: IN std_logic); +end component; + +-- Synplicity black box declaration +attribute syn_black_box : boolean; +attribute syn_black_box of ram_8x512: component is true; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : ram_8x512 + port map ( + addr => addr, + clk => clk, + din => din, + dout => dout, + en => en, + we => we); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file ram_8x512.vhd when simulating +-- the core, ram_8x512. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/coregen/ram_8x512.xco b/coregen/ram_8x512.xco new file mode 100644 index 0000000..0c99dca --- /dev/null +++ b/coregen/ram_8x512.xco @@ -0,0 +1,63 @@ +############################################################## +# +# Xilinx Core Generator version J.36 +# Date: Sat Jan 8 22:04:28 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc2v1000 +SET devicefamily = virtex2 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -6 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2 +# END Select +# BEGIN Parameters +CSET active_clock_edge=Rising_Edge_Triggered +CSET additional_output_pipe_stages=0 +CSET component_name=ram_8x512 +CSET depth=512 +CSET disable_warning_messages=true +CSET enable_pin=true +CSET enable_pin_polarity=Active_Low +CSET global_init_value=0 +CSET handshaking_pins=false +CSET has_limit_data_pitch=false +CSET init_pin=false +CSET init_value=0 +CSET initialization_pin_polarity=Active_High +CSET limit_data_pitch=18 +CSET load_init_file=false +CSET port_configuration=Read_And_Write +CSET primitive_selection=Optimize_For_Area +CSET register_inputs=false +CSET select_primitive=16kx1 +CSET width=8 +CSET write_enable_polarity=Active_Low +CSET write_mode=Read_After_Write +# END Parameters +GENERATE +# CRC: 85636b95 + diff --git a/coregen/ram_8x512_flist.txt b/coregen/ram_8x512_flist.txt new file mode 100644 index 0000000..6368a99 --- /dev/null +++ b/coregen/ram_8x512_flist.txt @@ -0,0 +1,9 @@ +# Output products list for +ram_8x512.vho +ram_8x512.asy +ram_8x512.sym +ram_8x512_xmdf.tcl +ram_8x512_flist.txt +ram_8x512.vhd +ram_8x512.ngc +ram_8x512.xco diff --git a/coregen/ram_8x512_readme.txt b/coregen/ram_8x512_readme.txt new file mode 100644 index 0000000..208d940 --- /dev/null +++ b/coregen/ram_8x512_readme.txt @@ -0,0 +1,41 @@ +The following files were generated for 'ram_8x512' in directory +coregen/: + +ram_8x512.vho: + VHO template file containing code that can be used as a model for + instantiating a CORE Generator module in a VHDL design. + +ram_8x512.asy: + Graphical symbol information file. Used by the ISE tools and some + third party tools to create a symbol representing the core. + +ram_8x512.sym: + Please see the core data sheet. + +ram_8x512_xmdf.tcl: + Please see the core data sheet. + +ram_8x512_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +ram_8x512.vhd: + VHDL wrapper file provided to support functional simulation. This + file contains simulation model customization data that is passed to + a parameterized simulation model for the core. + +ram_8x512.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +ram_8x512_readme.txt: + Text file indicating the files generated and how they are used. + +ram_8x512.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/coregen/ram_8x512_xmdf.tcl b/coregen/ram_8x512_xmdf.tcl new file mode 100644 index 0000000..80166dd --- /dev/null +++ b/coregen/ram_8x512_xmdf.tcl @@ -0,0 +1,72 @@ +# The package naming convention is _xmdf +package provide ram_8x512_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::ram_8x512_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::ram_8x512_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name ram_8x512 +} +# ::ram_8x512_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::ram_8x512_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.sym +utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ram_8x512.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module ram_8x512 +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/coregen/rom_8x2k.asy b/coregen/rom_8x2k.asy new file mode 100644 index 0000000..1a316f9 --- /dev/null +++ b/coregen/rom_8x2k.asy @@ -0,0 +1,27 @@ +Version 4 +SymbolType BLOCK +RECTANGLE Normal 32 0 320 272 +PIN 0 48 LEFT 36 +PINATTR PinName addr[10:0] +PINATTR Polarity IN +LINE Wide 0 48 32 48 +PIN 0 80 LEFT 36 +PINATTR PinName din[7:0] +PINATTR Polarity IN +LINE Wide 0 80 32 80 +PIN 0 112 LEFT 36 +PINATTR PinName we +PINATTR Polarity IN +LINE Normal 0 112 32 112 +PIN 0 144 LEFT 36 +PINATTR PinName en +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 240 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 352 48 RIGHT 36 +PINATTR PinName dout[7:0] +PINATTR Polarity OUT +LINE Wide 320 48 352 48 diff --git a/coregen/rom_8x2k.ngc b/coregen/rom_8x2k.ngc new file mode 100644 index 0000000..bd620f0 --- /dev/null +++ b/coregen/rom_8x2k.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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addr[10:0] +SYMPIN 0 80 Input din[7:0] +SYMPIN 0 112 Input we +SYMPIN 0 144 Input en +SYMPIN 0 240 Input clk +SYMPIN 352 48 Output dout[7:0] +RECTANGLE N 32 0 320 272 +BEGIN DISPLAY 36 48 PIN addr[10:0] ATTR PinName + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 0 48 32 48 +END LINE +BEGIN DISPLAY 36 80 PIN din[7:0] ATTR PinName + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 0 80 32 80 +END LINE +BEGIN DISPLAY 36 112 PIN we ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 112 32 112 +BEGIN DISPLAY 36 144 PIN en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 144 32 144 +BEGIN DISPLAY 36 240 PIN clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 240 32 240 +BEGIN DISPLAY 316 48 PIN dout[7:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 320 48 352 48 +END LINE +END SYMBOL diff --git a/coregen/rom_8x2k.vhd b/coregen/rom_8x2k.vhd new file mode 100644 index 0000000..07cc8aa --- /dev/null +++ b/coregen/rom_8x2k.vhd @@ -0,0 +1,113 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file rom_8x2k.vhd when simulating +-- the core, rom_8x2k. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY rom_8x2k IS + port ( + addr: IN std_logic_VECTOR(10 downto 0); + clk: IN std_logic; + din: IN std_logic_VECTOR(7 downto 0); + dout: OUT std_logic_VECTOR(7 downto 0); + en: IN std_logic; + we: IN std_logic); +END rom_8x2k; + +ARCHITECTURE rom_8x2k_a OF rom_8x2k IS +-- synthesis translate_off +component wrapped_rom_8x2k + port ( + addr: IN std_logic_VECTOR(10 downto 0); + clk: IN std_logic; + din: IN std_logic_VECTOR(7 downto 0); + dout: OUT std_logic_VECTOR(7 downto 0); + en: IN std_logic; + we: IN std_logic); +end component; + +-- Configuration specification + for all : wrapped_rom_8x2k use entity XilinxCoreLib.blkmemsp_v6_2(behavioral) + generic map( + c_sinit_value => "0", + c_has_en => 1, + c_reg_inputs => 0, + c_yclk_is_rising => 1, + c_ysinit_is_high => 1, + c_ywe_is_high => 0, + c_yprimitive_type => "16kx1", + c_ytop_addr => "1024", + c_yhierarchy => "hierarchy1", + c_has_limit_data_pitch => 0, + c_has_rdy => 0, + c_write_mode => 0, + c_width => 8, + c_yuse_single_primitive => 0, + c_has_nd => 0, + c_has_we => 1, + c_enable_rlocs => 0, + c_has_rfd => 0, + c_has_din => 1, + c_ybottom_addr => "0", + c_pipe_stages => 0, + c_yen_is_high => 0, + c_depth => 2048, + c_has_default_data => 1, + c_limit_data_pitch => 18, + c_has_sinit => 0, + c_yydisable_warnings => 1, + c_mem_init_file => "mif_file_16_1", + c_default_data => "0", + c_ymake_bmm => 0, + c_addr_width => 11); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_rom_8x2k + port map ( + addr => addr, + clk => clk, + din => din, + dout => dout, + en => en, + we => we); +-- synthesis translate_on + +END rom_8x2k_a; + diff --git a/coregen/rom_8x2k.vho b/coregen/rom_8x2k.vho new file mode 100644 index 0000000..787041b --- /dev/null +++ b/coregen/rom_8x2k.vho @@ -0,0 +1,66 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component rom_8x2k + port ( + addr: IN std_logic_VECTOR(10 downto 0); + clk: IN std_logic; + din: IN std_logic_VECTOR(7 downto 0); + dout: OUT std_logic_VECTOR(7 downto 0); + en: IN std_logic; + we: IN std_logic); +end component; + +-- Synplicity black box declaration +attribute syn_black_box : boolean; +attribute syn_black_box of rom_8x2k: component is true; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : rom_8x2k + port map ( + addr => addr, + clk => clk, + din => din, + dout => dout, + en => en, + we => we); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file rom_8x2k.vhd when simulating +-- the core, rom_8x2k. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/coregen/rom_8x2k.xco b/coregen/rom_8x2k.xco new file mode 100644 index 0000000..c4ed2d3 --- /dev/null +++ b/coregen/rom_8x2k.xco @@ -0,0 +1,63 @@ +############################################################## +# +# Xilinx Core Generator version J.36 +# Date: Sat Jan 8 22:04:43 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc2v1000 +SET devicefamily = virtex2 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -6 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2 +# END Select +# BEGIN Parameters +CSET active_clock_edge=Rising_Edge_Triggered +CSET additional_output_pipe_stages=0 +CSET component_name=rom_8x2k +CSET depth=2048 +CSET disable_warning_messages=true +CSET enable_pin=true +CSET enable_pin_polarity=Active_Low +CSET global_init_value=0 +CSET handshaking_pins=false +CSET has_limit_data_pitch=false +CSET init_pin=false +CSET init_value=0 +CSET initialization_pin_polarity=Active_High +CSET limit_data_pitch=18 +CSET load_init_file=false +CSET port_configuration=Read_And_Write +CSET primitive_selection=Optimize_For_Area +CSET register_inputs=false +CSET select_primitive=16kx1 +CSET width=8 +CSET write_enable_polarity=Active_Low +CSET write_mode=Read_After_Write +# END Parameters +GENERATE +# CRC: d4bb4e0b + diff --git a/coregen/rom_8x2k_flist.txt b/coregen/rom_8x2k_flist.txt new file mode 100644 index 0000000..2323760 --- /dev/null +++ b/coregen/rom_8x2k_flist.txt @@ -0,0 +1,9 @@ +# Output products list for +rom_8x2k_xmdf.tcl +rom_8x2k_flist.txt +rom_8x2k.sym +rom_8x2k.xco +rom_8x2k.vho +rom_8x2k.asy +rom_8x2k.ngc +rom_8x2k.vhd diff --git a/coregen/rom_8x2k_readme.txt b/coregen/rom_8x2k_readme.txt new file mode 100644 index 0000000..a58c42f --- /dev/null +++ b/coregen/rom_8x2k_readme.txt @@ -0,0 +1,41 @@ +The following files were generated for 'rom_8x2k' in directory +coregen/: + +rom_8x2k_xmdf.tcl: + Please see the core data sheet. + +rom_8x2k_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +rom_8x2k.sym: + Please see the core data sheet. + +rom_8x2k.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +rom_8x2k.vho: + VHO template file containing code that can be used as a model for + instantiating a CORE Generator module in a VHDL design. + +rom_8x2k_readme.txt: + Text file indicating the files generated and how they are used. + +rom_8x2k.asy: + Graphical symbol information file. Used by the ISE tools and some + third party tools to create a symbol representing the core. + +rom_8x2k.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +rom_8x2k.vhd: + VHDL wrapper file provided to support functional simulation. This + file contains simulation model customization data that is passed to + a parameterized simulation model for the core. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/coregen/rom_8x2k_xmdf.tcl b/coregen/rom_8x2k_xmdf.tcl new file mode 100644 index 0000000..9346f7f --- /dev/null +++ b/coregen/rom_8x2k_xmdf.tcl @@ -0,0 +1,72 @@ +# The package naming convention is _xmdf +package provide rom_8x2k_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::rom_8x2k_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::rom_8x2k_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name rom_8x2k +} +# ::rom_8x2k_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::rom_8x2k_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.sym +utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path rom_8x2k.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module rom_8x2k +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/memory.bmm b/memory.bmm new file mode 100644 index 0000000..3705b54 --- /dev/null +++ b/memory.bmm @@ -0,0 +1,21 @@ +ADDRESS_SPACE blockrom RAMB16 [0xf000:0xffff] + + BUS_BLOCK + + rom_8x2k_lo/B8 [7:0]; + rom_8x2k_hi/B8 [15:8]; + + END_BUS_BLOCK; + +END_ADDRESS_SPACE; + +ADDRESS_SPACE blockram RAMB16 [0x0200:0x11ff] + + BUS_BLOCK + + ram_8x512_lo/B8 [7:0]; + ram_8x512_hi/B8 [15:8]; + + END_BUS_BLOCK; + +END_ADDRESS_SPACE; diff --git a/openMSP430_defines.v b/openMSP430_defines.v new file mode 100644 index 0000000..a6904fb --- /dev/null +++ b/openMSP430_defines.v @@ -0,0 +1,447 @@ +//---------------------------------------------------------------------------- +// Copyright (C) 2001 Authors +// +// This source file may be used and distributed without restriction provided +// that this copyright statement is not removed from the file and that any +// derivative work contains the original copyright notice and the associated +// disclaimer. +// +// This source file is free software; you can redistribute it and/or modify +// it under the terms of the GNU Lesser General Public License as published +// by the Free Software Foundation; either version 2.1 of the License, or +// (at your option) any later version. +// +// This source is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public +// License for more details. +// +// You should have received a copy of the GNU Lesser General Public License +// along with this source; if not, write to the Free Software Foundation, +// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +// +//---------------------------------------------------------------------------- +// +// *File Name: openMSP430_defines.v +// +// *Module Description: +// openMSP430 Configuration file +// +// *Author(s): +// - Olivier Girard, olgirard@gmail.com +// +//---------------------------------------------------------------------------- +// $Rev: 74 $ +// $LastChangedBy: olivier.girard $ +// $LastChangedDate: 2010-08-28 21:53:08 +0200 (Sat, 28 Aug 2010) $ +//---------------------------------------------------------------------------- +`include "openMSP430_undefines.v" + +//---------------------------------------------------------------------------- +// SYSTEM CONFIGURATION +//---------------------------------------------------------------------------- +// +// Note: the sum of both program and data memories should not exceed 63.5 kB +// + +// Program Memory Size: +// Uncomment the required memory size +//------------------------------------------------------- +//`define PMEM_SIZE_59_KB +//`define PMEM_SIZE_55_KB +//`define PMEM_SIZE_54_KB +//`define PMEM_SIZE_51_KB +//`define PMEM_SIZE_48_KB +//`define PMEM_SIZE_41_KB +//`define PMEM_SIZE_32_KB +//`define PMEM_SIZE_24_KB +//`define PMEM_SIZE_16_KB +//`define PMEM_SIZE_12_KB +//`define PMEM_SIZE_8_KB +`define PMEM_SIZE_4_KB +//`define PMEM_SIZE_2_KB +//`define PMEM_SIZE_1_KB + +// Data Memory Size: +// Uncomment the required memory size +//------------------------------------------------------- +//`define DMEM_SIZE_32_KB +//`define DMEM_SIZE_24_KB +//`define DMEM_SIZE_16_KB +//`define DMEM_SIZE_10_KB +//`define DMEM_SIZE_8_KB +//`define DMEM_SIZE_5_KB +//`define DMEM_SIZE_4_KB +//`define DMEM_SIZE_2p5_KB +//`define DMEM_SIZE_2_KB +`define DMEM_SIZE_1_KB +//`define DMEM_SIZE_512_B +//`define DMEM_SIZE_256_B +//`define DMEM_SIZE_128_B + + +// Include/Exclude Hardware Multiplier +`define MULTIPLIER + + +//---------------------------------------------------------------------------- +// REMOTE DEBUGGING INTERFACE CONFIGURATION +//---------------------------------------------------------------------------- + +// Include Debug interface +//`define DBG_EN + +// Debug interface selection +// `define DBG_UART -> Enable UART (8N1) debug interface +// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED +// +//`define DBG_UART +//`define DBG_JTAG + +// Number of hardware breakpoints (each unit contains 2 hw address breakpoints) +// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0 +// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1 +// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2 +// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3 +// +//`define DBG_HWBRK_0 +//`define DBG_HWBRK_1 +//`define DBG_HWBRK_2 +//`define DBG_HWBRK_3 + + +//==========================================================================// +//==========================================================================// +//==========================================================================// +//==========================================================================// +//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====// +//==========================================================================// +//==========================================================================// +//==========================================================================// +//==========================================================================// + +// +// PROGRAM & DATA MEMORY CONFIGURATION +//====================================== + +// Program Memory Size +`ifdef PMEM_SIZE_59_KB + `define PMEM_AWIDTH 15 + `define PMEM_SIZE 60416 +`endif +`ifdef PMEM_SIZE_55_KB + `define PMEM_AWIDTH 15 + `define PMEM_SIZE 56320 +`endif +`ifdef PMEM_SIZE_54_KB + `define PMEM_AWIDTH 15 + `define PMEM_SIZE 55296 +`endif +`ifdef PMEM_SIZE_51_KB + `define PMEM_AWIDTH 15 + `define PMEM_SIZE 52224 +`endif +`ifdef PMEM_SIZE_48_KB + `define PMEM_AWIDTH 15 + `define PMEM_SIZE 49152 +`endif +`ifdef PMEM_SIZE_41_KB + `define PMEM_AWIDTH 15 + `define PMEM_SIZE 41984 +`endif +`ifdef PMEM_SIZE_32_KB + `define PMEM_AWIDTH 14 + `define PMEM_SIZE 32768 +`endif +`ifdef PMEM_SIZE_24_KB + `define PMEM_AWIDTH 14 + `define PMEM_SIZE 24576 +`endif +`ifdef PMEM_SIZE_16_KB + `define PMEM_AWIDTH 13 + `define PMEM_SIZE 16384 +`endif +`ifdef PMEM_SIZE_12_KB + `define PMEM_AWIDTH 13 + `define PMEM_SIZE 12288 +`endif +`ifdef PMEM_SIZE_8_KB + `define PMEM_AWIDTH 12 + `define PMEM_SIZE 8192 +`endif +`ifdef PMEM_SIZE_4_KB + `define PMEM_AWIDTH 11 + `define PMEM_SIZE 4096 +`endif +`ifdef PMEM_SIZE_2_KB + `define PMEM_AWIDTH 10 + `define PMEM_SIZE 2048 +`endif +`ifdef PMEM_SIZE_1_KB + `define PMEM_AWIDTH 9 + `define PMEM_SIZE 1024 +`endif + +// Data Memory Size +`ifdef DMEM_SIZE_32_KB + `define DMEM_AWIDTH 14 + `define DMEM_SIZE 32768 +`endif +`ifdef DMEM_SIZE_24_KB + `define DMEM_AWIDTH 14 + `define DMEM_SIZE 24576 +`endif +`ifdef DMEM_SIZE_16_KB + `define DMEM_AWIDTH 13 + `define DMEM_SIZE 16384 +`endif +`ifdef DMEM_SIZE_10_KB + `define DMEM_AWIDTH 13 + `define DMEM_SIZE 10240 +`endif +`ifdef DMEM_SIZE_8_KB + `define DMEM_AWIDTH 12 + `define DMEM_SIZE 8192 +`endif +`ifdef DMEM_SIZE_5_KB + `define DMEM_AWIDTH 12 + `define DMEM_SIZE 5120 +`endif +`ifdef DMEM_SIZE_4_KB + `define DMEM_AWIDTH 11 + `define DMEM_SIZE 4096 +`endif +`ifdef DMEM_SIZE_2p5_KB + `define DMEM_AWIDTH 11 + `define DMEM_SIZE 2560 +`endif +`ifdef DMEM_SIZE_2_KB + `define DMEM_AWIDTH 10 + `define DMEM_SIZE 2048 +`endif +`ifdef DMEM_SIZE_1_KB + `define DMEM_AWIDTH 9 + `define DMEM_SIZE 1024 +`endif +`ifdef DMEM_SIZE_512_B + `define DMEM_AWIDTH 8 + `define DMEM_SIZE 512 +`endif +`ifdef DMEM_SIZE_256_B + `define DMEM_AWIDTH 7 + `define DMEM_SIZE 256 +`endif +`ifdef DMEM_SIZE_128_B + `define DMEM_AWIDTH 6 + `define DMEM_SIZE 128 +`endif + +// Data Memory Base Adresses +`define DMEM_BASE 16'h0200 + +// Program & Data Memory most significant address bit (for 16 bit words) +`define PMEM_MSB `PMEM_AWIDTH-1 +`define DMEM_MSB `DMEM_AWIDTH-1 + +// +// STATES, REGISTER FIELDS, ... +//====================================== + +// Instructions type +`define INST_SO 0 +`define INST_JMP 1 +`define INST_TO 2 + +// Single-operand arithmetic +`define RRC 0 +`define SWPB 1 +`define RRA 2 +`define SXT 3 +`define PUSH 4 +`define CALL 5 +`define RETI 6 +`define IRQ 7 + +// Conditional jump +`define JNE 0 +`define JEQ 1 +`define JNC 2 +`define JC 3 +`define JN 4 +`define JGE 5 +`define JL 6 +`define JMP 7 + +// Two-operand arithmetic +`define MOV 0 +`define ADD 1 +`define ADDC 2 +`define SUBC 3 +`define SUB 4 +`define CMP 5 +`define DADD 6 +`define BIT 7 +`define BIC 8 +`define BIS 9 +`define XOR 10 +`define AND 11 + +// Addressing modes +`define DIR 0 +`define IDX 1 +`define INDIR 2 +`define INDIR_I 3 +`define SYMB 4 +`define IMM 5 +`define ABS 6 +`define CONST 7 + +// Execution state machine +`define E_IRQ_0 4'h0 +`define E_IRQ_1 4'h1 +`define E_IRQ_2 4'h2 +`define E_IRQ_3 4'h3 +`define E_IRQ_4 4'h4 +`define E_SRC_AD 4'h5 +`define E_SRC_RD 4'h6 +`define E_SRC_WR 4'h7 +`define E_DST_AD 4'h8 +`define E_DST_RD 4'h9 +`define E_DST_WR 4'hA +`define E_EXEC 4'hB +`define E_JUMP 4'hC +`define E_IDLE 4'hD + +// ALU control signals +`define ALU_SRC_INV 0 +`define ALU_INC 1 +`define ALU_INC_C 2 +`define ALU_ADD 3 +`define ALU_AND 4 +`define ALU_OR 5 +`define ALU_XOR 6 +`define ALU_DADD 7 +`define ALU_STAT_7 8 +`define ALU_STAT_F 9 +`define ALU_SHIFT 10 +`define EXEC_NO_WR 11 + +// Debug interface +`define DBG_UART_WR 18 +`define DBG_UART_BW 17 +`define DBG_UART_ADDR 16:11 + +// Debug interface CPU_CTL register +`define HALT 0 +`define RUN 1 +`define ISTEP 2 +`define SW_BRK_EN 3 +`define FRZ_BRK_EN 4 +`define RST_BRK_EN 5 +`define CPU_RST 6 + +// Debug interface CPU_STAT register +`define HALT_RUN 0 +`define PUC_PND 1 +`define SWBRK_PND 3 +`define HWBRK0_PND 4 +`define HWBRK1_PND 5 + +// Debug interface BRKx_CTL register +`define BRK_MODE_RD 0 +`define BRK_MODE_WR 1 +`define BRK_MODE 1:0 +`define BRK_EN 2 +`define BRK_I_EN 3 +`define BRK_RANGE 4 + +// Basic clock module: BCSCTL1 Control Register +`define DIVAx 5:4 + +// Basic clock module: BCSCTL2 Control Register +`define SELS 3 +`define DIVSx 2:1 + +// Timer A: TACTL Control Register +`define TASSELx 9:8 +`define TAIDx 7:6 +`define TAMCx 5:4 +`define TACLR 2 +`define TAIE 1 +`define TAIFG 0 + +// Timer A: TACCTLx Capture/Compare Control Register +`define TACMx 15:14 +`define TACCISx 13:12 +`define TASCS 11 +`define TASCCI 10 +`define TACAP 8 +`define TAOUTMODx 7:5 +`define TACCIE 4 +`define TACCI 3 +`define TAOUT 2 +`define TACOV 1 +`define TACCIFG 0 + + +// +// DEBUG INTERFACE EXTRA CONFIGURATION +//====================================== + +// Debug interface: Software breakpoint opcode +`define DBG_SWBRK_OP 16'h4343 + +// Debug UART interface auto data synchronization +// If the following define is commented out, then +// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly +// defined. +`define DBG_UART_AUTO_SYNC + +// Debug UART interface data rate +// In order to properly setup the UART debug interface, you +// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and +// the chosen BAUD rate from the UART interface. +// +//`define DBG_UART_BAUD 9600 +//`define DBG_UART_BAUD 19200 +//`define DBG_UART_BAUD 38400 +//`define DBG_UART_BAUD 57600 +//`define DBG_UART_BAUD 115200 +//`define DBG_UART_BAUD 230400 +//`define DBG_UART_BAUD 460800 +//`define DBG_UART_BAUD 576000 +//`define DBG_UART_BAUD 921600 +`define DBG_UART_BAUD 2000000 +`define DBG_DCO_FREQ 20000000 +`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1) + +// Enable/Disable the hardware breakpoint RANGE mode +`define HWBRK_RANGE 1'b0 + +// Counter width for the debug interface UART +`define DBG_UART_XFER_CNT_W 16 + +// Check configuration +`ifdef DBG_EN + `ifdef DBG_UART + `ifdef DBG_JTAG +CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED + `endif + `else + `ifdef DBG_JTAG +CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED + `else +CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED + `endif + `endif +`endif + +// +// MULTIPLIER CONFIGURATION +//====================================== + +// If uncommented, the following define selects +// the 16x16 multiplier (1 cycle) instead of the +// default 16x8 multplier (2 cycles) +//`define MPY_16x16 + diff --git a/openMSP430_uart.prj b/openMSP430_uart.prj new file mode 100644 index 0000000..d17fdd7 --- /dev/null +++ b/openMSP430_uart.prj @@ -0,0 +1,26 @@ +verilog work openmsp430/omsp_alu.v +verilog work openmsp430/omsp_clock_module.v +verilog work openmsp430/omsp_dbg.v +verilog work openmsp430/omsp_dbg_hwbrk.v +verilog work openmsp430/omsp_dbg_uart.v +verilog work openmsp430/omsp_execution_unit.v +verilog work openmsp430/omsp_frontend.v +verilog work openmsp430/omsp_mem_backbone.v +verilog work openmsp430/omsp_multiplier.v +verilog work openmsp430/omsp_register_file.v +verilog work openmsp430/omsp_sfr.v +verilog work openmsp430/omsp_watchdog.v +verilog work openmsp430/openMSP430.v +verilog work openmsp430/openMSP430_undefines.v +verilog work openmsp430/timescale.v + +verilog work openMSP430_defines.v + +verilog work openmsp430/periph/omsp_gpio.v +verilog work openmsp430/periph/omsp_timerA.v + +vhdl work coregen/ram_8x512.vhd +vhdl work coregen/rom_8x2k.vhd + +vhdl work openMSP430_uart.vhd + diff --git a/openMSP430_uart.ucf b/openMSP430_uart.ucf new file mode 100644 index 0000000..7649e6c --- /dev/null +++ b/openMSP430_uart.ucf @@ -0,0 +1,31 @@ +#==============================================================================# +# Clock & Reset # +#==============================================================================# + +# V munualu jsou piny prohozeny! +#NET "CLK_100MHz" LOC = "B11" | PERIOD = 10.0 ns LOW 5.0 ns; +NET "CLK_24MHz" LOC = "A11" | PERIOD = 41.7 ns LOW 20.9 ns; + +NET "RESET" LOC = "B6"; + + +#==============================================================================# +# 7-Segment Display # +#==============================================================================# + +NET "DISPLAY1<0>" LOC = "D9"; +NET "DISPLAY1<1>" LOC = "C9"; +NET "DISPLAY1<2>" LOC = "F11"; +NET "DISPLAY1<3>" LOC = "F9"; +NET "DISPLAY1<4>" LOC = "F10"; +NET "DISPLAY1<5>" LOC = "D10"; +NET "DISPLAY1<6>" LOC = "C10"; + +NET "DISPLAY2<0>" LOC = "B9"; +NET "DISPLAY2<1>" LOC = "A8"; +NET "DISPLAY2<2>" LOC = "B8"; +NET "DISPLAY2<3>" LOC = "E7"; +NET "DISPLAY2<4>" LOC = "E8"; +NET "DISPLAY2<5>" LOC = "E10"; +NET "DISPLAY2<6>" LOC = "E9"; + diff --git a/openMSP430_uart.vhd b/openMSP430_uart.vhd new file mode 100644 index 0000000..f1fa1c2 --- /dev/null +++ b/openMSP430_uart.vhd @@ -0,0 +1,262 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity openMSP430_uart is + port ( + CLK_24MHz: in std_logic; + RESET: in std_logic; + DISPLAY1: out std_logic_vector(6 downto 0); + DISPLAY2: out std_logic_vector(6 downto 0) + ); +end openMSP430_uart; + +-------------------------------------------------------------------------------- + +architecture rtl of openMSP430_uart is + component openMSP430 is + port( + aclk_en : out std_logic; -- ACLK enable + dbg_freeze : out std_logic; -- Freeze peripherals + dbg_uart_txd : out std_logic; -- Debug interface: UART TXD + dmem_addr : out std_logic_vector (8 downto 0); -- Data Memory address + dmem_cen : out std_logic; -- Data Memory chip enable (low active) + dmem_din : out std_logic_vector (15 downto 0); -- Data Memory data input + dmem_wen : out std_logic_vector (1 downto 0); -- Data Memory write enable (low active) + irq_acc : out std_logic_vector (13 downto 0); -- Interrupt request accepted (one-hot signal) + mclk : out std_logic; -- Main system clock + per_addr : out std_logic_vector (7 downto 0); -- Peripheral address + per_din : out std_logic_vector (15 downto 0); -- Peripheral data input + per_wen : out std_logic_vector (1 downto 0); -- Peripheral write enable (high active) + per_en : out std_logic; -- Peripheral enable (high active) + pmem_addr : out std_logic_vector (10 downto 0); -- Program Memory address + pmem_cen : out std_logic; -- Program Memory chip enable (low active) + pmem_din : out std_logic_vector (15 downto 0); -- Program Memory data input (optional) + pmem_wen : out std_logic_vector (1 downto 0); -- Program Memory write enable (low active) (optional) + puc : out std_logic; -- Main system reset + smclk_en : out std_logic; -- SMCLK enable + + dbg_uart_rxd : in std_logic; -- Debug interface: UART RXD + dco_clk : in std_logic; -- Fast oscillator (fast clock) + dmem_dout : in std_logic_vector (15 downto 0); -- Data Memory data output + irq : in std_logic_vector (13 downto 0); -- Maskable interrupts + lfxt_clk : in std_logic; -- Low frequency oscillator (typ 32kHz) + nmi : in std_logic; -- Non-maskable interrupt (asynchronous) + per_dout : in std_logic_vector (15 downto 0); -- Peripheral data output + pmem_dout : in std_logic_vector (15 downto 0); -- Program Memory data output + reset_n : in std_logic -- Reset Pin (low active) + ); + end component; + + component ram_8x512 + port ( + addr: in std_logic_VECTOR(8 downto 0); + clk: in std_logic; + din: in std_logic_VECTOR(7 downto 0); + dout: out std_logic_VECTOR(7 downto 0); + en: in std_logic; + we: in std_logic + ); + end component; + + component rom_8x2k + port ( + addr: in std_logic_VECTOR(10 downto 0); + clk: in std_logic; + din: in std_logic_VECTOR(7 downto 0); + dout: out std_logic_VECTOR(7 downto 0); + en: in std_logic; + we: in std_logic + ); + end component; + + + component omsp_gpio + generic ( + P1_EN : std_logic; + P2_EN : std_logic; + P3_EN : std_logic; + P4_EN : std_logic; + P5_EN : std_logic; + P6_EN : std_logic + ); + port( + mclk : in std_logic; + p1_din : in std_logic_vector(7 downto 0); + p2_din : in std_logic_vector(7 downto 0); + p3_din : in std_logic_vector(7 downto 0); + p4_din : in std_logic_vector(7 downto 0); + p5_din : in std_logic_vector(7 downto 0); + p6_din : in std_logic_vector(7 downto 0); + per_addr : in std_logic_vector(7 downto 0); + per_din : in std_logic_vector(15 downto 0); + per_en : in std_logic; + per_wen : in std_logic_vector(1 downto 0); + puc : in std_logic; + irq_port1 : out std_logic; + irq_port2 : out std_logic; + p1_dout : out std_logic_vector(7 downto 0); + p1_dout_en : out std_logic_vector(7 downto 0); + p1_sel : out std_logic_vector(7 downto 0); + p2_dout : out std_logic_vector(7 downto 0); + p2_dout_en : out std_logic_vector(7 downto 0); + p2_sel : out std_logic_vector(7 downto 0); + p3_dout : out std_logic_vector(7 downto 0); + p3_dout_en : out std_logic_vector(7 downto 0); + p3_sel : out std_logic_vector(7 downto 0); + p4_dout : out std_logic_vector(7 downto 0); + p4_dout_en : out std_logic_vector(7 downto 0); + p4_sel : out std_logic_vector(7 downto 0); + p5_dout : out std_logic_vector(7 downto 0); + p5_dout_en : out std_logic_vector(7 downto 0); + p5_sel : out std_logic_vector(7 downto 0); + p6_dout : out std_logic_vector(7 downto 0); + p6_dout_en : out std_logic_vector(7 downto 0); + p6_sel : out std_logic_vector(7 downto 0); + per_dout : out std_logic_vector(15 downto 0) + ); + end component; + + + signal mclk : std_logic; + signal puc : std_logic; + + signal pmem_addr : std_logic_vector (10 downto 0); + signal pmem_dout : std_logic_vector (15 downto 0); + signal pmem_cen : std_logic; + + signal dmem_addr : std_logic_vector (8 downto 0); + signal dmem_cen : std_logic; + signal dmem_wen : std_logic_vector (1 downto 0); + signal dmem_din : std_logic_vector (15 downto 0); + signal dmem_dout : std_logic_vector (15 downto 0); + + signal per_din : std_logic_vector (15 downto 0); + signal per_dout : std_logic_Vector (15 downto 0); + signal per_wen : std_logic_vector (1 downto 0); + signal per_en : std_logic; + signal per_addr : std_logic_vector (7 downto 0); + +-------------------------------------------------------------------------------- + +begin + openMSP430_0 : openMSP430 port map ( + aclk_en => open, + dbg_freeze => open, + dbg_uart_txd => open, + dmem_addr => dmem_addr, + dmem_cen => dmem_cen, + dmem_din => dmem_din, + dmem_wen => dmem_wen, + irq_acc => open, + mclk => mclk, + per_addr => per_addr, + per_din => per_din, + per_wen => per_wen, + per_en => per_en, + pmem_addr => pmem_addr, + pmem_cen => pmem_cen, + pmem_din => open, + pmem_wen => open, + puc => puc, + smclk_en => open, + + dbg_uart_rxd => '0', + dco_clk => CLK_24MHz, + dmem_dout => dmem_dout, + irq => (others => '0'), + lfxt_clk => '0', + nmi => '0', + per_dout => per_dout, + pmem_dout => pmem_dout, + reset_n => RESET + ); + + ram_8x512_hi : ram_8x512 port map ( + addr => dmem_addr, + clk => mclk, + din => dmem_din (15 downto 8), + dout => dmem_dout (15 downto 8), + en => dmem_cen, + we => dmem_wen (1) + ); + + ram_8x512_lo : ram_8x512 port map ( + addr => dmem_addr, + clk => mclk, + din => dmem_din (7 downto 0), + dout => dmem_dout (7 downto 0), + en => dmem_cen, + we => dmem_wen (0) + ); + + rom_8x2k_hi : rom_8x2k port map ( + addr => pmem_addr, + clk => mclk, + din => (others => '0'), + dout => pmem_dout (15 downto 8), + en => pmem_cen, + we => '1' + ); + + rom_8x2k_lo : rom_8x2k port map ( + addr => pmem_addr, + clk => mclk, + din => (others => '0'), + dout => pmem_dout (7 downto 0), + en => pmem_cen, + we => '1' + ); + + + omsp_gpio_0 : omsp_gpio + generic map ( + P1_EN => '1', -- Enable Port 1 + P2_EN => '1', -- Enable Port 2 + P3_EN => '0', -- Enable Port 3 + P4_EN => '0', -- Enable Port 4 + P5_EN => '0', -- Enable Port 5 + P6_EN => '0' -- Enable Port 6 + ) + port map ( + irq_port1 => open, + irq_port2 => open, + p1_dout (6 downto 0) => DISPLAY1, + p1_dout (7) => open, + p1_dout_en => open, + p1_sel => open, + p2_dout (6 downto 0) => DISPLAY2, + p2_dout (7) => open, + p2_dout_en => open, + p2_sel => open, + p3_dout => open, + p3_dout_en => open, + p3_sel => open, + p4_dout => open, + p4_dout_en => open, + p4_sel => open, + p5_dout => open, + p5_dout_en => open, + p5_sel => open, + p6_dout => open, + p6_dout_en => open, + p6_sel => open, + per_dout => per_dout, + mclk => mclk, + p1_din => (others => '0'), + p2_din => (others => '0'), + p3_din => (others => '0'), + p4_din => (others => '0'), + p5_din => (others => '0'), + p6_din => (others => '0'), + per_addr => per_addr, + per_din => per_din, + per_en => per_en, + per_wen => per_wen, + puc => puc + ); + + +end rtl; + diff --git a/software/README.txt b/software/README.txt new file mode 100644 index 0000000..79c251c --- /dev/null +++ b/software/README.txt @@ -0,0 +1,47 @@ +what's this? +------------ +it's a simple example project for the MSP430 series MCU and the GCC port +of the mspgcc project. the project contains a makefile and uses assembler +and C sources. this time it is a software UART with Timer_A. + +this example shows the following features: + - Timer_A uart, full duplex + o same pins as BSL (P1.1 TX, P2.2 RX) + o it contains a reusable code + + - software FLL + the watch crystal is used as reference and the main clock + is adjusted to 1.536MHz on startup + + - use uprintf to print formated strings and do a printf + emulation that prints to the serial port. + + - the main loop is a simple line editor. when a return character + ('\r', usualy RETURN key) is received, it writes the received + characters from the buffer to the serial port. + connect a terminal at 9600,N,8,1 to try it out. + + - makefile + o compile and link + o include assembler files + o convert to intel hex format + o generate a listing with mixed C / assembly + +required hardware +----------------- + + - a MSP430F1121 or larger device (any from the F1x series) + connect pins P1.1 (TX) and P2.2 (RX) through level converters + to a terminal. you can also use a BSL hardware, the same pins + are used. + + - watch crystal 32.768kHz + + - optionaly a LED on P2.5 (470 Ohms series resistor to GND) + +disclaimer +---------- +this example is part of the mspgcc project http://mspgcc.sf.net +see license.txt for details. + +chris \ No newline at end of file diff --git a/software/fll.h b/software/fll.h new file mode 100644 index 0000000..6740ca8 --- /dev/null +++ b/software/fll.h @@ -0,0 +1,6 @@ +#ifndef FLL_H +#define FLL_H + +void fllInit(void); //do an FLL loop to adjust system frequency + +#endif //FLL_H diff --git a/software/fll.s b/software/fll.s new file mode 100644 index 0000000..49e02c2 --- /dev/null +++ b/software/fll.s @@ -0,0 +1,51 @@ +#include "hardware.h" +.text +.global fllInit ; SW FLL to init DCO/SMCLK -frequency + .type fllInit, @function +fllInit: + mov.b #BCSCTL1_FLL, &BCSCTL1 ; Init basic clock control reg 1 + mov.b #BCSCTL2_FLL, &BCSCTL2 ; Init basic clock control reg 2 + mov #TACTL_FLL, &TACTL ; SMCLK is TA-clock / Timer stopped + bis #MC1, &TACTL ; Start timer: Continuos Mode + mov #CCTL2_FLL, &CCTL2 ; Init CCR2 and Clear capture flag + +.Lwait0:bit #CCIFG, &CCTL2 ; Test/Wait for capture flag + jz .Lwait0 ; May be used with INT / LPM0 later ? + mov &CCR2, r15 ; Store CCR2 init-value + bic #CCIFG, &CCTL2 ; Clear capture flag +.Lwait1:bit #CCIFG, &CCTL2 ; Test/Wait for capture flag + jz .Lwait1 ; May be used with INT / LPM0 later ? + bic #CCIFG, &CCTL2 ; Clear capture flag + mov.b &BCSCTL1, r14 ; Store current Rsel value + bic.b #0x0f8, r14 ; Mask for Rsel bits + mov.b &DCOCTL, r13 ; Store current DCO value + +.LfllUP:cmp.b #DCOCTL_MAX, r13 ; Needs Rsel to be increased ? + jne .LfllDN ; No + cmp.b #7, r14 ; Is max Rsel already selected ? + jge .LfllER ; Yes, Rsel can not be increased + inc.b &BCSCTL1 ; Increase Rsel + jmp .LfllRx ; Test DCO again + +.LfllDN:cmp.b #DCOCTL_MIN, r13 ; Needs Rsel to be decreased ? + jne .LfllCP ; No + cmp.b #0, r14 ; Is min Rsel already selected ? + jeq .LfllER ; Yes, Rsel can not be increased + dec.b &BCSCTL1 ; Decrease Rsel +.LfllRx:mov.b #60h, &DCOCTL ; Center DCO (may be optimized later ?) + jmp .Lwait0 ; Test DCO again +.LfllCP: + mov &CCR2, r12 ; Read captured value + sub r15, r12 ; Subtract last captured value + mov &CCR2, r15 ; Store CCR2 value for next pass + cmp #DCO_FSET, r12 ; DCO_FSET= SMCLK/(32768/4) + jl .LfllI ; + jeq .LfllOK ; +.LfllD: dec.b &DCOCTL ; Decrement value + jmp .Lwait0 ; +.LfllI: inc.b &DCOCTL ; Increment value + jmp .Lwait0 ; + +.LfllER: ; error, currently ingnored +.LfllOK:clr &CCTL2 ; stop CCR2 + ret ; diff --git a/software/hardware.h b/software/hardware.h new file mode 100644 index 0000000..a586ac3 --- /dev/null +++ b/software/hardware.h @@ -0,0 +1,72 @@ +#ifndef HARDWARE_H +#define HARDWARE_H + +#define __msp430_have_port3 +#define __MSP430_HAS_PORT3__ + +#include +#include +#include + + +//PINS +//PORT1 +#define TX BIT1 + +//PORT2 +#define RX BIT2 +#define LED BIT1 + +//Port Output Register 'P1OUT, P2OUT': +#define P1OUT_INIT TX //Init Output data of port1 +#define P2OUT_INIT 0 //Init Output data of port2 +#define P3OUT_INIT 0 //Init Output data of port3 + +//Port Direction Register 'P1DIR, P2DIR': +#define P1DIR_INIT TX //Init of Port1 Data-Direction Reg (Out=1 / Inp=0) +#define P2DIR_INIT ~RX //Init of Port2 Data-Direction Reg (Out=1 / Inp=0) +#define P3DIR_INIT 0xff //Init of Port3 Data-Direction Reg (Out=1 / Inp=0) + +//Selection of Port or Module -Function on the Pins 'P1SEL, P2SEL' +#define P1SEL_INIT 0 //P1-Modules: +#define P2SEL_INIT RX //P2-Modules: +#define P3SEL_INIT 0 //P3-Modules: + +//Interrupt capabilities of P1 and P2 +#define P1IE_INIT 0 //Interrupt Enable (0=dis 1=enabled) +#define P2IE_INIT 0 //Interrupt Enable (0=dis 1=enabled) +#define P1IES_INIT 0 //Interrupt Edge Select (0=pos 1=neg) +#define P2IES_INIT 0 //Interrupt Edge Select (0=pos 1=neg) + +#define IE_INIT 0 +#define WDTCTL_INIT WDTPW|WDTHOLD + +#define BCSCTL1_FLL XT2OFF|DIVA1|RSEL2|RSEL0 +#define BCSCTL2_FLL 0 +#define TACTL_FLL TASSEL_2|TACLR +#define CCTL2_FLL CM0|CCIS0|CAP + +#define TACTL_AFTER_FLL TASSEL_2|TACLR|ID_0 + +//#define BAUD 40 //9600 @3MHz div 8 +//#define BAUD 20 //19200 @3MHz div 8 +//#define BAUD 20 //9600 @1.5MHz div 8 +//#define BAUD 140 //9600 @1.5MHz div 8 + +//#define BAUD 2083 //9600 @20.0MHz div 1 +//#define BAUD 1042 //19200 @20.0MHz div 1 +//#define BAUD 521 //38400 @20.0MHz div 1 +//#define BAUD 347 //57600 @20.0MHz div 1 +#define BAUD 174 //115200 @20.0MHz div 1 +//#define BAUD 87 //230400 @20.0MHz div 1 + +//Selection of 'Digitally Controlled Oszillator' (desired frquency in HZ, 1..3 MHz) +#define DCO_FREQ 1536000 //3072000/2 makes 9600 a bit more precise + +//Automatic, do not edit +#define DCO_FSET (DCO_FREQ/8192) //DCO_FSET = DCO_FREQ / (32768/4) +#define DCOCTL_MAX 0xff // Used from FLL to check when Rsel must be changed +#define DCOCTL_MIN 0 // Used from FLL to check when Rsel must be changed + + +#endif //HARDWARE_H diff --git a/software/main.c b/software/main.c new file mode 100644 index 0000000..7655138 --- /dev/null +++ b/software/main.c @@ -0,0 +1,106 @@ +/* +see README.txt for details. + +chris +*/ +#include "hardware.h" +#include +#include +#include "swuart.h" +#include "fll.h" + +/** +Delay function. +*/ +void delay(unsigned int d) { + while(d--) { + nop(); + nop(); + } +} + +/** +Main function with init an an endless loop that is synced with the +interrupts trough the lowpower mode. +*/ +int main(void) { + int reading = 0; + int pos = 0; + char buf[40]; + int led = 0; + + WDTCTL = WDTCTL_INIT; //Init watchdog timer + + P1OUT = P1OUT_INIT; //Init output data of port1 + P1SEL = P1SEL_INIT; //Select port or module -function on port1 + P1DIR = P1DIR_INIT; //Init port direction register of port1 + P1IES = P1IES_INIT; //init port interrupts + P1IE = P1IE_INIT; + + P2OUT = P2OUT_INIT; //Init output data of port2 + P2SEL = P2SEL_INIT; //Select port or module -function on port2 + P2DIR = P2DIR_INIT; //Init port direction register of port2 + P2IES = P2IES_INIT; //init port interrupts + P2IE = P2IE_INIT; + + P3DIR = 0xff; + P3OUT = 0xff; //light LED during init + delay(65535); //Wait for watch crystal startup + delay(65535); +// fllInit(); //Init FLL to desired frequency using the 32k768 cystal as reference. + P3OUT = 0x00; //switch off LED + + TACTL = TACTL_AFTER_FLL; //setup timer (still stopped) + CCTL0 = CCIE|CAP|CM_2|CCIS_1|SCS; //select P2.2 with UART signal + CCTL1 = 0; // + CCTL2 = 0; // + TACTL |= MC1; //start timer + + eint(); //enable interrupts + + printf("\r\n====== openMSP430 in action ======\r\n"); //say hello + printf("\r\nSimple Line Editor Ready\r\n"); //say hello + + while (1) { //main loop, never ends... + printf("> "); //show prompt + reading = 1; + while (reading) { //loop and read characters + LPM0; //sync, wakeup by irq + + led++; // Some lighting... + if (led==9) { + led = 0; + } + P3OUT = (0x01 << led); + + switch (rxdata) { + //process RETURN key + case '\r': + //case '\n': + printf("\r\n"); //finish line + buf[pos++] = 0; //to use printf... + printf(":%s\r\n", buf); + reading = 0; //exit read loop + pos = 0; //reset buffer + break; + //backspace + case '\b': + if (pos > 0) { //is there a char to delete? + pos--; //remove it in buffer + putchar('\b'); //go back + putchar(' '); //erase on screen + putchar('\b'); //go back + } + break; + //other characters + default: + //only store characters if buffer has space + if (pos < sizeof(buf)) { + putchar(rxdata); //echo + buf[pos++] = rxdata; //store + } + } + } + } +} + diff --git a/software/makefile b/software/makefile new file mode 100644 index 0000000..ca0bdb8 --- /dev/null +++ b/software/makefile @@ -0,0 +1,55 @@ +# makfile configuration +NAME = ta_uart +OBJECTS = main.o swuart.o fll.o +CPU = msp430x1121 + +ASFLAGS = -mmcu=${CPU} -mforce-hwmul -x assembler-with-cpp -D_GNU_ASSEMBLER_ -c +CFLAGS = -mmcu=${CPU} -mforce-hwmul -O2 -Wall -g + +#switch the compiler (for the internal make rules) +CC = msp430-gcc +AS = msp430-gcc + +.PHONY: all FORCE clean download download-jtag download-bsl dist + +#all should be the first target. it's built when make is runwithout args +all: ${NAME}.elf ${NAME}.a43 ${NAME}.lst + +#confgigure the next line if you want to use the serial download +download: download-uart +#download: download-jtag +#download: download-bsl + +#additional rules for files +${NAME}.elf: ${OBJECTS} + ${CC} -mmcu=${CPU} -o $@ ${OBJECTS} + +${NAME}.a43: ${NAME}.elf + msp430-objcopy -O ihex $^ $@ + +${NAME}.lst: ${NAME}.elf + msp430-objdump -dSt $^ > $@ + +download-jtag: all + msp430-jtag -e ${NAME}.elf + +download-bsl: all + msp430-bsl -e ${NAME}.elf + +download-uart: all + openmsp430-loader.tcl -device /dev/ttyUSB0 -baudrate 115200 ${NAME}.elf + +clean: + rm -f ${NAME} ${NAME}.a43 ${NAME}.lst *.o + +#backup archive +dist: + tar czf dist.tgz *.c *.h *.txt makefile + +#dummy target as dependecy if something has to be build everytime +FORCE: + +#project dependencies +main.o: main.c hardware.h +fll.o: fll.s hardware.h +swuart.o: swuart.s hardware.h diff --git a/software/miniterm.py b/software/miniterm.py new file mode 100644 index 0000000..d0bd887 --- /dev/null +++ b/software/miniterm.py @@ -0,0 +1,135 @@ +#!/usr/bin/env python +#very simple serial terminal +#http://pyserial.sf.net package required +#input characters are sent directly, received characters are displays as is +#baudrate and echo configuartion is done through globals: + +# + +import sys, os, serial, threading, getopt +#EXITCHARCTER = '\x1b' #ESC +EXITCHARCTER = '\x04' #ctrl+d + +#first choosea platform dependant way to read single characters from the console +if os.name == 'nt': #sys.platform == 'win32': + import msvcrt + def getkey(): + while 1: + if echo: + z = msvcrt.getche() + else: + z = msvcrt.getch() + if z == '\0' or z == '\xe0': #functions keys + msvcrt.getch() + else: + return z + +elif os.name == 'posix': + #XXX: Untested code derrived from the Python FAQ.... +# import termios, TERMIOS, sys, os + import termios, sys, os + fd = sys.stdin.fileno() + old = termios.tcgetattr(fd) + new = termios.tcgetattr(fd) + new[3] = new[3] & ~TERMIOS.ICANON & ~TERMIOS.ECHO + new[6][TERMIOS.VMIN] = 1 + new[6][TERMIOS.VTIME] = 0 + termios.tcsetattr(fd, TERMIOS.TCSANOW, new) + s = '' # We'll save the characters typed and add them to the pool. + def getkey(): + c = os.read(fd, 1) + if echo: sys.stdout.write(c) + return c + def clenaup_console(): + termios.tcsetattr(fd, TERMIOS.TCSAFLUSH, old) + sys.exitfunc = clenaup_console #terminal modes have to be restored on exit... + +else: + raise "Sorry no implementation for your platform (%s) available." % sys.platform + + +def reader(): + """loop forever and copy serial->console""" + while 1: + sys.stdout.write(s.read()) + +def writer(): + """loop forever and copy console->serial""" + while 1: + c = getkey() + if c == EXITCHARCTER: break #exit on esc + s.write(c) #send character + if convert_outgoing_cr and c == '\r': + s.write('\n') + if echo: sys.stdout.write('\n') + + +#print a short help message +def usage(): + print >>sys.stderr, """USAGE: %s [options] + Simple Terminal Programm for the serial port. + + options: + -p, --port=PORT: port, a number, defualt = 0 or a device name + -b, --baud=BAUD: baudrate, default 9600 + -r, --rtscts: enable RTS/CTS flow control (default off) + -x, --xonxoff: enable software flow control (default off) + -e, --echo: enable local echo (default off) + -c, --cr: disable CR -> CR+LF translation + + """ % sys.argv[0] + +if __name__ == '__main__': + #parse command line options + try: + opts, args = getopt.getopt(sys.argv[1:], + "hp:b:rxec", + ["help", "port=", "baud=", "rtscts", "xonxoff", "echo", "cr"]) + except getopt.GetoptError: + # print help information and exit: + usage() + sys.exit(2) + + port = 0 + baudrate = 9600 + echo = 0 + convert_outgoing_cr = 1 + rtscts = 0 + xonxoff = 0 + for o, a in opts: + if o in ("-h", "--help"): #help text + usage() + sys.exit() + elif o in ("-p", "--port"): #specified port + try: + port = int(a) + except ValueError: + port = a + elif o in ("-b", "--baud"): #specified baudrate + try: + baudrate = int(a) + except ValueError: + raise ValueError, "Baudrate must be a integer number" + elif o in ("-r", "--rtscts"): + rtscts = 1 + elif o in ("-x", "--xonxoff"): + xonxoff = 1 + elif o in ("-e", "--echo"): + echo = 1 + elif o in ("-c", "--cr"): + convert_outgoing_cr = 0 + + try: + s = serial.Serial(port, baudrate, rtscts=rtscts, xonxoff=xonxoff) + except: + print "could not open port" + sys.exit(1) + print "--- Miniterm --- type Ctrl-D to quit" + #start serial->console thread + r = threading.Thread(target=reader) + r.setDaemon(1) + r.start() + #enter console->serial loop + writer() + + print "\n--- exit ---" diff --git a/software/swuart.h b/software/swuart.h new file mode 100644 index 0000000..140712f --- /dev/null +++ b/software/swuart.h @@ -0,0 +1,6 @@ +#ifndef SWUART_H +#define SWUART_H + +void serPutc(char); //send one character over timer_a uart +extern char rxdata; +#endif //SWUART_H diff --git a/software/swuart.s b/software/swuart.s new file mode 100644 index 0000000..dc17823 --- /dev/null +++ b/software/swuart.s @@ -0,0 +1,78 @@ +#include "hardware.h" + +;variables +.data + .comm rxdata,1,1 ;char var + .comm rxshift,1,1 ;char var + .comm rxbit,2,2 ;short var, aligned + +.text + +interrupt(TIMERA0_VECTOR) ;register interrupt vector +;interrupt handler to receive as Timer_A UART +.global ccr0 ;place a label afterwards so +ccr0: ;that it is used in the listing + add rxbit, r0 + jmp .Lrxstart ;start bit + jmp .Lrxdatabit ;D0 + jmp .Lrxdatabit ;D1 + jmp .Lrxdatabit ;D2 + jmp .Lrxdatabit ;D3 + jmp .Lrxdatabit ;D4 + jmp .Lrxdatabit ;D5 + jmp .Lrxdatabit ;D6 +; jmp .Lrxlastbit ;D7 that one is following anyway + +.Lrxlastbit: ;last bit, handle byte + bit #SCCI, &CCTL0 ;read last bit + rrc.b rxshift ;and save it + clr rxbit ;reset state + mov #CCIE|CAP|CM_2|CCIS_1|SCS, &CCTL0 ;restore capture mode + mov.b rxshift, rxdata ;copy received data + bic #CPUOFF|OSCOFF|SCG0|SCG1, 0(r1) ;exit all lowpower modes + ;here you might do other things too, like setting a flag + ;that the wakeup comes from the Timer_A UART. however + ;it should not take longer than one bit time, otherwise + ;charcetrs will be lost. + reti + +.Lrxstart: ;startbit, init + clr rxshift ;clear input buffer + add #(BAUD/2), &CCR0 ;startbit + 1.5 bits -> first bit + mov #CCIE|CCIS_1|SCS, &CCTL0;set compare mode, sample bits + jmp .Lrxex ;set state,... + +.Lrxdatabit: ;save databit + bit #SCCI, &CCTL0 ;measure databit + rrc.b rxshift ;rotate in databit + +.Lrxex: add #BAUD, &CCR0 ;one bit delay + incd rxbit ;setup next state + reti + +; void serPutc(char) +;use an other Capture/Compare than for receiving (full duplex). +;this one is without interrupts and OUTMOD, because only +;this way P1.1 can be used. P1.1 is prefered because the +;BSL is on that pin too. +.global putchar + .type putchar, @function +putchar: ;send a byte + mov #0, &CCTL1 ;select compare mode + mov #10, r13 ;ten bits: Start, 8 Data, Stop + rla r15 ;shift in start bit (0) + bis #0x0200, r15 ;set tenth bit (1), thats the stop bit + mov &TAR, &CCR1 ;set up start time +.Lt1lp: add #BAUD, &CCR1 ;set up for one bit + rrc r15 ;shift data trough carry + jc .Lt1 ;test carry bit +.Lt0: bic.b #TX, &P1OUT ;generate pulse + jmp .Ltc ; +.Lt1: bis.b #TX, &P1OUT ;just use the same amount of time as for a zero + jmp .Ltc ; +.Ltc: bit #CCIFG, &CCTL1 ;wait for compare + jz .Ltc ;loop until the bit is set + bic #CCIFG, &CCTL1 ;clear for next loop + dec r13 ;decrement bit counter + jnz .Lt1lp ;loop until all bits are transmitted + ret