X-Git-Url: http://rtime.felk.cvut.cz/gitweb/fpga/virtex2/uart.git/blobdiff_plain/04325406ee353e690bad026b6961ed6331c1ab0d..a24f1edd0b700eb64b3e56835af9a69f926ac0d6:/openMSP430_uart.prj

diff --git a/openMSP430_uart.prj b/openMSP430_uart.prj
new file mode 100644
index 0000000..d17fdd7
--- /dev/null
+++ b/openMSP430_uart.prj
@@ -0,0 +1,26 @@
+verilog work openmsp430/omsp_alu.v
+verilog work openmsp430/omsp_clock_module.v
+verilog work openmsp430/omsp_dbg.v
+verilog work openmsp430/omsp_dbg_hwbrk.v
+verilog work openmsp430/omsp_dbg_uart.v
+verilog work openmsp430/omsp_execution_unit.v
+verilog work openmsp430/omsp_frontend.v
+verilog work openmsp430/omsp_mem_backbone.v
+verilog work openmsp430/omsp_multiplier.v
+verilog work openmsp430/omsp_register_file.v
+verilog work openmsp430/omsp_sfr.v
+verilog work openmsp430/omsp_watchdog.v
+verilog work openmsp430/openMSP430.v
+verilog work openmsp430/openMSP430_undefines.v
+verilog work openmsp430/timescale.v
+
+verilog work openMSP430_defines.v
+
+verilog work openmsp430/periph/omsp_gpio.v
+verilog work openmsp430/periph/omsp_timerA.v
+
+vhdl work coregen/ram_8x512.vhd
+vhdl work coregen/rom_8x2k.vhd
+
+vhdl work openMSP430_uart.vhd
+