The following files were generated for 'ram_8x512' in directory 
coregen/:

ram_8x512.vho:
   VHO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a VHDL design.

ram_8x512.asy:
   Graphical symbol information file. Used by the ISE tools and some
   third party tools to create a symbol representing the core.

ram_8x512.sym:
   Please see the core data sheet.

ram_8x512_xmdf.tcl:
   Please see the core data sheet.

ram_8x512_flist.txt:
   Text file listing all of the output files produced when a customized
   core was generated in the CORE Generator.

ram_8x512.vhd:
   VHDL wrapper file provided to support functional simulation. This
   file contains simulation model customization data that is passed to
   a parameterized simulation model for the core.

ram_8x512.ngc:
   Binary Xilinx implementation netlist file containing the information
   required to implement the module in a Xilinx (R) FPGA.

ram_8x512_readme.txt:
   Text file indicating the files generated and how they are used.

ram_8x512.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.


Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.