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#
# Xilinx Core Generator version J.36
# Date: Sat Jan  8 22:04:43 2011
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc2v1000
SET devicefamily = virtex2
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fg456
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -6
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET active_clock_edge=Rising_Edge_Triggered
CSET additional_output_pipe_stages=0
CSET component_name=rom_8x2k
CSET depth=2048
CSET disable_warning_messages=true
CSET enable_pin=true
CSET enable_pin_polarity=Active_Low
CSET global_init_value=0
CSET handshaking_pins=false
CSET has_limit_data_pitch=false
CSET init_pin=false
CSET init_value=0
CSET initialization_pin_polarity=Active_High
CSET limit_data_pitch=18
CSET load_init_file=false
CSET port_configuration=Read_And_Write
CSET primitive_selection=Optimize_For_Area
CSET register_inputs=false
CSET select_primitive=16kx1
CSET width=8
CSET write_enable_polarity=Active_Low
CSET write_mode=Read_After_Write
# END Parameters
GENERATE
# CRC: d4bb4e0b