#==============================================================================#
# Clock & Reset                                                                #
#==============================================================================#

NET "CLK_24MHz"         LOC = "A11" |     PERIOD =  41.7 ns LOW  20.9 ns;

NET "RESET_N"           LOC = "B6";


#==============================================================================#
# RS-232 Port                                                                  #
#==============================================================================#

NET "TXD"               LOC = "A7";     # output from the board (from FPGA)
NET "RXD"               LOC = "B7";     # input to the board (to FPGA)