From: Vladimir Burian <buriavl2@fel.cvut.cz>
Date: Wed, 18 May 2011 20:46:03 +0000 (+0200)
Subject: Improper top module signals initialization.
X-Git-Url: http://rtime.felk.cvut.cz/gitweb/fpga/virtex2/msp_motion.git/commitdiff_plain/5003c3b6cc021dc3377b51c8c21f439a46b072aa?hp=078d4db12fc9133712b65b45c22863be28175074

Improper top module signals initialization.
---

diff --git a/msp_motion.vhd b/msp_motion.vhd
index 2e94987..b131d18 100644
--- a/msp_motion.vhd
+++ b/msp_motion.vhd
@@ -62,6 +62,7 @@ architecture rtl of msp_motion is
   signal per_en    : std_logic;
   signal per_addr  : std_logic_vector (7 downto 0);
   -- Interrupt
+  --signal irq       : std_logic_vector (13 downto 0) := (others => '0');
   signal irq       : std_logic_vector (13 downto 0);
   signal irq_acc   : std_logic_vector (13 downto 0);
 
@@ -89,7 +90,7 @@ architecture rtl of msp_motion is
   signal DPA_SEL     : std_logic;
   signal DPA_STB     : std_logic;
   -- Auxiliary register used to generate IRF_ACK
-  signal IRF_ACK_REG : std_logic;
+  signal IRF_ACK_REG : std_logic := '0';
   -- Auxiliary signal used to form B-port address
   signal DPB_ADR     : std_logic_vector (9 downto 0);