library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--------------------------------------------------------------------------------

entity msp_motion is
  port (
    -- Clock & reset
    CLK_24MHz : in  std_logic;
    RESET     : in  std_logic;
    -- RS232
    RXD       : in  std_logic;
    TXD       : out std_logic;
    -- LED
    LED0      : out std_logic;
    LED1      : out std_logic;
    LED2      : out std_logic;
    -- PWM
    PWM0      : out std_logic;
    PWM0_EN   : out std_logic;
    PWM1      : out std_logic;
    PWM1_EN   : out std_logic;
    PWM2      : out std_logic;
    PWM2_EN   : out std_logic;
    -- IRC
    IRC_INDEX : in  std_logic;
    IRC_A     : in  std_logic;
    IRC_B     : in  std_logic;
    -- HALL
    HAL0      : in  std_logic;
    HAL1      : in  std_logic;
    HAL2      : in  std_logic);
end msp_motion;

--------------------------------------------------------------------------------

architecture rtl of msp_motion is

  -- OpenMSP430 softcore MCU module
  signal mclk     : std_logic;
  signal puc      : std_logic;
  
--------------------------------------------------------------------------------

begin
  
  ------------------------------------------------------------------------------
  -- OpenMSP430 softcore MCU module
  ------------------------------------------------------------------------------
  openMSP430_1 : entity work.openMSP430_8_32_mul_dbus
    port map (
      dco_clk                  => CLK_24MHz,
      lfxt_clk                 => '0',
      reset_n                  => RESET,
      rxd                      => RXD,
      txd                      => TXD,
      per_addr                 => open,
      per_din                  => open,
      per_dout                 => (others => '0'),
      per_wen                  => open,
      per_en                   => open,
      nmi                      => '0',
      irq                      => (others => '0'),
      irq_acc                  => open,
      aclk_en                  => open,
      smclk_en                 => open,
      mclk                     => mclk,
      puc                      => puc,
      dmem_addr                => open,
      dmem_ce                  => open,
      dmem_we                  => open,
      dmem_din                 => open,
      dmem_dout                => (others => '0'));
  
end rtl;