library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity openMSP430_fpga is port ( CLK_24MHz: in std_logic; RESET: in std_logic; DISPLAY1: out std_logic_vector(6 downto 0); DISPLAY2: out std_logic_vector(6 downto 0) ); end openMSP430_fpga; -------------------------------------------------------------------------------- architecture rtl of openMSP430_fpga is component openMSP430 is port( aclk_en : out std_logic; -- ACLK enable dbg_freeze : out std_logic; -- Freeze peripherals dbg_uart_txd : out std_logic; -- Debug interface: UART TXD dmem_addr : out std_logic_vector (8 downto 0); -- Data Memory address dmem_cen : out std_logic; -- Data Memory chip enable (low active) dmem_din : out std_logic_vector (15 downto 0); -- Data Memory data input dmem_wen : out std_logic_vector (1 downto 0); -- Data Memory write enable (low active) irq_acc : out std_logic_vector (13 downto 0); -- Interrupt request accepted (one-hot signal) mclk : out std_logic; -- Main system clock per_addr : out std_logic_vector (7 downto 0); -- Peripheral address per_din : out std_logic_vector (15 downto 0); -- Peripheral data input per_wen : out std_logic_vector (1 downto 0); -- Peripheral write enable (high active) per_en : out std_logic; -- Peripheral enable (high active) pmem_addr : out std_logic_vector (10 downto 0); -- Program Memory address pmem_cen : out std_logic; -- Program Memory chip enable (low active) pmem_din : out std_logic_vector (15 downto 0); -- Program Memory data input (optional) pmem_wen : out std_logic_vector (1 downto 0); -- Program Memory write enable (low active) (optional) puc : out std_logic; -- Main system reset smclk_en : out std_logic; -- SMCLK enable dbg_uart_rxd : in std_logic; -- Debug interface: UART RXD dco_clk : in std_logic; -- Fast oscillator (fast clock) dmem_dout : in std_logic_vector (15 downto 0); -- Data Memory data output irq : in std_logic_vector (13 downto 0); -- Maskable interrupts lfxt_clk : in std_logic; -- Low frequency oscillator (typ 32kHz) nmi : in std_logic; -- Non-maskable interrupt (asynchronous) per_dout : in std_logic_vector (15 downto 0); -- Peripheral data output pmem_dout : in std_logic_vector (15 downto 0); -- Program Memory data output reset_n : in std_logic -- Reset Pin (low active) ); end component; component ram_8x512 port ( addr: in std_logic_VECTOR(8 downto 0); clk: in std_logic; din: in std_logic_VECTOR(7 downto 0); dout: out std_logic_VECTOR(7 downto 0); en: in std_logic; we: in std_logic ); end component; component rom_8x2k port ( addr: in std_logic_VECTOR(10 downto 0); clk: in std_logic; din: in std_logic_VECTOR(7 downto 0); dout: out std_logic_VECTOR(7 downto 0); en: in std_logic; we: in std_logic ); end component; component omsp_gpio generic ( P1_EN : std_logic; P2_EN : std_logic; P3_EN : std_logic; P4_EN : std_logic; P5_EN : std_logic; P6_EN : std_logic ); port( mclk : in std_logic; p1_din : in std_logic_vector(7 downto 0); p2_din : in std_logic_vector(7 downto 0); p3_din : in std_logic_vector(7 downto 0); p4_din : in std_logic_vector(7 downto 0); p5_din : in std_logic_vector(7 downto 0); p6_din : in std_logic_vector(7 downto 0); per_addr : in std_logic_vector(7 downto 0); per_din : in std_logic_vector(15 downto 0); per_en : in std_logic; per_wen : in std_logic_vector(1 downto 0); puc : in std_logic; irq_port1 : out std_logic; irq_port2 : out std_logic; p1_dout : out std_logic_vector(7 downto 0); p1_dout_en : out std_logic_vector(7 downto 0); p1_sel : out std_logic_vector(7 downto 0); p2_dout : out std_logic_vector(7 downto 0); p2_dout_en : out std_logic_vector(7 downto 0); p2_sel : out std_logic_vector(7 downto 0); p3_dout : out std_logic_vector(7 downto 0); p3_dout_en : out std_logic_vector(7 downto 0); p3_sel : out std_logic_vector(7 downto 0); p4_dout : out std_logic_vector(7 downto 0); p4_dout_en : out std_logic_vector(7 downto 0); p4_sel : out std_logic_vector(7 downto 0); p5_dout : out std_logic_vector(7 downto 0); p5_dout_en : out std_logic_vector(7 downto 0); p5_sel : out std_logic_vector(7 downto 0); p6_dout : out std_logic_vector(7 downto 0); p6_dout_en : out std_logic_vector(7 downto 0); p6_sel : out std_logic_vector(7 downto 0); per_dout : out std_logic_vector(15 downto 0) ); end component; signal mclk : std_logic; signal puc : std_logic; signal pmem_addr : std_logic_vector (10 downto 0); signal pmem_dout : std_logic_vector (15 downto 0); signal pmem_cen : std_logic; signal dmem_addr : std_logic_vector (8 downto 0); signal dmem_cen : std_logic; signal dmem_wen : std_logic_vector (1 downto 0); signal dmem_din : std_logic_vector (15 downto 0); signal dmem_dout : std_logic_vector (15 downto 0); signal per_din : std_logic_vector (15 downto 0); signal per_dout : std_logic_Vector (15 downto 0); signal per_wen : std_logic_vector (1 downto 0); signal per_en : std_logic; signal per_addr : std_logic_vector (7 downto 0); -------------------------------------------------------------------------------- begin openMSP430_0 : openMSP430 port map ( aclk_en => open, dbg_freeze => open, dbg_uart_txd => open, dmem_addr => dmem_addr, dmem_cen => dmem_cen, dmem_din => dmem_din, dmem_wen => dmem_wen, irq_acc => open, mclk => mclk, per_addr => per_addr, per_din => per_din, per_wen => per_wen, per_en => per_en, pmem_addr => pmem_addr, pmem_cen => pmem_cen, pmem_din => open, pmem_wen => open, puc => puc, smclk_en => open, dbg_uart_rxd => '0', dco_clk => CLK_24MHz, dmem_dout => dmem_dout, irq => (others => '0'), lfxt_clk => '0', nmi => '0', per_dout => per_dout, pmem_dout => pmem_dout, reset_n => RESET ); ram_8x512_hi : ram_8x512 port map ( addr => dmem_addr, clk => mclk, din => dmem_din (15 downto 8), dout => dmem_dout (15 downto 8), en => dmem_cen, we => dmem_wen (1) ); ram_8x512_lo : ram_8x512 port map ( addr => dmem_addr, clk => mclk, din => dmem_din (7 downto 0), dout => dmem_dout (7 downto 0), en => dmem_cen, we => dmem_wen (0) ); rom_8x2k_hi : rom_8x2k port map ( addr => pmem_addr, clk => mclk, din => (others => '0'), dout => pmem_dout (15 downto 8), en => pmem_cen, we => '1' ); rom_8x2k_lo : rom_8x2k port map ( addr => pmem_addr, clk => mclk, din => (others => '0'), dout => pmem_dout (7 downto 0), en => pmem_cen, we => '1' ); omsp_gpio_0 : omsp_gpio generic map ( P1_EN => '1', -- Enable Port 1 P2_EN => '1', -- Enable Port 2 P3_EN => '0', -- Enable Port 3 P4_EN => '0', -- Enable Port 4 P5_EN => '0', -- Enable Port 5 P6_EN => '0' -- Enable Port 6 ) port map ( irq_port1 => open, irq_port2 => open, p1_dout (6 downto 0) => DISPLAY1, p1_dout (7) => open, p1_dout_en => open, p1_sel => open, p2_dout (6 downto 0) => DISPLAY2, p2_dout (7) => open, p2_dout_en => open, p2_sel => open, p3_dout => open, p3_dout_en => open, p3_sel => open, p4_dout => open, p4_dout_en => open, p4_sel => open, p5_dout => open, p5_dout_en => open, p5_sel => open, p6_dout => open, p6_dout_en => open, p6_sel => open, per_dout => per_dout, mclk => mclk, p1_din => (others => '0'), p2_din => (others => '0'), p3_din => (others => '0'), p4_din => (others => '0'), p5_din => (others => '0'), p6_din => (others => '0'), per_addr => per_addr, per_din => per_din, per_en => per_en, per_wen => per_wen, puc => puc ); end rtl;