From c6a65ad432f6d0b7f941632755d1433cd3724864 Mon Sep 17 00:00:00 2001 From: Vladimir Burian Date: Thu, 27 Jan 2011 20:56:22 +0100 Subject: [PATCH] Some comments added. --- baud_gen.vhd | 21 +++++++++++++++++++++ fifo.vhd | 30 ++++++++++++++++++++++++------ tx.vhd | 19 ++++++++++++++++--- tx_control.vhd | 7 +++++++ 4 files changed, 68 insertions(+), 9 deletions(-) diff --git a/baud_gen.vhd b/baud_gen.vhd index 20f8010..e778c71 100644 --- a/baud_gen.vhd +++ b/baud_gen.vhd @@ -3,6 +3,27 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; +-------------------------------------------------------------------------------- +-- Baud generator is an adjustable clock frequency divider. Division factor +-- is determined by the value present on the input vector named 'scale' and is +-- equal to: +-- f_OUT = f_IN / (2 * (1 + 'scale')) +-- +-- The divided clock signal has a duty cycle of 50%. +-- +-- The reset input signal is asynchronous. When held active, the output is 0. +-- When released, the output starts a new period and goes high with the next +-- rising edge of the input clock signal. +-- +-- _ _ _ _ _ _ _ _ _ _ _ _ +-- CLK _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_ +-- _________ +-- RESET ____________| |__________________________ +-- ___ __ ___ ___ ___ +-- CLK_BAUD _| |___| |____________| |___| |___| |___ +-- +-------------------------------------------------------------------------------- + entity baud_gen is generic ( SCALE_WIDTH : integer := 16 diff --git a/fifo.vhd b/fifo.vhd index 04213f1..ae3ca9e 100644 --- a/fifo.vhd +++ b/fifo.vhd @@ -3,6 +3,21 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; +-------------------------------------------------------------------------------- +-- This is a behavioral model of FIFO (Fisrt In First Out) memory. +-- +-- All operations (except for reset) are synchronous to 'clk' rising edges. +-- Reset makes fifo empty but actually does not change the content of memory. +-- +-- The generic parameter 'width' determines the width of address vector used to +-- access memory and so the size of memory. +-- +-- When overflow occurs, the 'overflow' flag is set to 1 and the least recent +-- data is rewritten by new data. +-- +-- Underflow is not handled currently and causes misfunction. +-------------------------------------------------------------------------------- + entity fifo is generic ( width : integer := 2 @@ -10,14 +25,14 @@ entity fifo is port ( clk : in std_logic; reset : in std_logic; - we : in std_logic; - re : in std_logic; - clear_ow : in std_logic; + we : in std_logic; -- write enable + re : in std_logic; -- read enable + clear_ow : in std_logic; -- clear overflow flag d_in : in std_logic_vector (7 downto 0); d_out : out std_logic_vector (7 downto 0); - full : out std_logic; - hfull : out std_logic; - empty : out std_logic; + full : out std_logic; -- fifo is full + hfull : out std_logic; -- fifo is half full + empty : out std_logic; -- fifo is empty overflow : out std_logic ); end fifo; @@ -42,6 +57,8 @@ architecture behavioral of fifo is begin + -- Handling of overflow output signal and internal length signal, storing + -- the number of occupied memory positions. process (clk, reset) begin if (reset = '1') then @@ -66,6 +83,7 @@ begin end process; + -- Handling of address registers and writing to memory. process (clk, reset) begin if (reset = '1') then diff --git a/tx.vhd b/tx.vhd index aca961a..ccf9a86 100644 --- a/tx.vhd +++ b/tx.vhd @@ -3,6 +3,19 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; +-------------------------------------------------------------------------------- +-- Output shift register +-- +-- This entity can be used for generating of RS232 like output. Configuration is +-- hard wired as 8N1 (8 bits of data, no parity, 1 stop bit). +-- +-- All operations (except for 'reset') are synchronous to 'clk' rising edges. +-- This clock signal also determines baud rate. +-- +-- When 'ready' signal is high, next data vector can be written in by setting +-- 'we' signal. +-------------------------------------------------------------------------------- + entity transmitter is port ( clk : in std_logic; @@ -16,14 +29,14 @@ end transmitter; -------------------------------------------------------------------------------- -architecture dataflow of transmitter is +architecture behavioral of transmitter is -- Output shift register (containing also start and stop bit). signal tx_shift_reg : std_logic_vector (9 downto 0); -- Register parallel to the output shift register where '1' shows the last -- bit of the frame ('1' is in the place of stop bit). signal tx_flag : std_logic_vector (9 downto 0); - -- Transmitting of new frame could be started with next tx_clk. + -- Transmitting of new frame could be started with next clk. signal tx_ready : std_logic; -------------------------------------------------------------------------------- @@ -61,5 +74,5 @@ begin tx <= tx_shift_reg(0); -end dataflow; +end behavioral; diff --git a/tx_control.vhd b/tx_control.vhd index 155605b..d7c4f25 100644 --- a/tx_control.vhd +++ b/tx_control.vhd @@ -3,6 +3,13 @@ use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; +-------------------------------------------------------------------------------- +-- Transmitter control FSM +-- +-- Finite state machine controlling interconnection of FIFO buffer and output +-- shift register. +-------------------------------------------------------------------------------- + entity tx_control is port ( clk : in std_logic; -- 2.39.2