From: Vladimir Burian <buriavl2@fel.cvut.cz>
Date: Wed, 18 May 2011 19:37:06 +0000 (+0200)
Subject: Early initialization of all relevant signals.
X-Git-Url: http://rtime.felk.cvut.cz/gitweb/fpga/uart.git/commitdiff_plain/6ce709d167d1e0f4b0ab62ad931b737ea781136a

Early initialization of all relevant signals.

Now it is not required to do reset after start-up.
---

diff --git a/baud_gen.vhd b/baud_gen.vhd
index 81dfa5c..f3312f0 100644
--- a/baud_gen.vhd
+++ b/baud_gen.vhd
@@ -47,8 +47,8 @@ end baud_gen;
 
 architecture behavioral of baud_gen is
 
-  signal counter    : std_logic_vector (SCALE_WIDTH-1 downto 0);
-  signal clk_baud_s : std_logic;
+  signal counter    : std_logic_vector (SCALE_WIDTH-1 downto 0) := (others => '0');
+  signal clk_baud_s : std_logic := '0';
 
 --------------------------------------------------------------------------------
 
diff --git a/fifo.vhd b/fifo.vhd
index ae3ca9e..f59a438 100644
--- a/fifo.vhd
+++ b/fifo.vhd
@@ -33,7 +33,7 @@ entity fifo is
     full     : out std_logic;  -- fifo is full
     hfull    : out std_logic;  -- fifo is half full
     empty    : out std_logic;  -- fifo is empty
-    overflow : out std_logic
+    overflow : out std_logic := '0'
   );
 end fifo;
 
@@ -46,10 +46,10 @@ architecture behavioral of fifo is
 
   signal memory : mem_t;
   
-  signal read_addr : mem_addr_t;
-  signal write_addr : mem_addr_t;
+  signal read_addr : mem_addr_t := (others => '0');
+  signal write_addr : mem_addr_t := (others => '0');
 
-  signal length : std_logic_vector (width downto 0);
+  signal length : std_logic_vector (width downto 0) := (others => '0');
 
   signal full_s : std_logic;
 
diff --git a/rx.vhd b/rx.vhd
index 11dc9d9..db1c132 100644
--- a/rx.vhd
+++ b/rx.vhd
@@ -32,8 +32,8 @@ entity receiver is
     en            : in  std_logic;
     rx            : in  std_logic;
     ready         : out std_logic;
-    bad_start_bit : out std_logic;
-    bad_stop_bit  : out std_logic;
+    bad_start_bit : out std_logic := '0';
+    bad_stop_bit  : out std_logic := '0';
     data          : out std_logic_vector (7 downto 0));
 end entity receiver;
 
@@ -43,8 +43,8 @@ architecture behavioral of receiver is
   
   signal rx_shift_reg : std_logic_vector (9 downto 0);
   signal rx_flag      : std_logic_vector (9 downto 0);
-  signal rx_ready     : std_logic;
-  signal rx_running   : std_logic;
+  signal rx_ready     : std_logic := '1';
+  signal rx_running   : std_logic := '0';
   
 --------------------------------------------------------------------------------
   
diff --git a/rx_control.vhd b/rx_control.vhd
index ad10c6d..80904fa 100644
--- a/rx_control.vhd
+++ b/rx_control.vhd
@@ -11,10 +11,10 @@ entity rx_control is
     bad_start_bit : in  std_logic;
     bad_stop_bit  : in  std_logic;
     rx_ready      : in  std_logic;
-    rx_reset      : out std_logic;
-    rx_en         : out std_logic;
-    fifo_we       : out std_logic;
-    clk_en        : out std_logic);
+    rx_reset      : out std_logic := '0';
+    rx_en         : out std_logic := '0';
+    fifo_we       : out std_logic := '0';
+    clk_en        : out std_logic := '0');
 end entity rx_control;
 
 --------------------------------------------------------------------------------
@@ -23,7 +23,7 @@ architecture behavioral of rx_control is
 
   type state_t is (resetting, waiting, next_frame, receiving);
 
-  signal state : state_t;
+  signal state : state_t := waiting;
 
 --------------------------------------------------------------------------------
 
diff --git a/tx.vhd b/tx.vhd
index ccf9a86..278d6b8 100644
--- a/tx.vhd
+++ b/tx.vhd
@@ -32,12 +32,12 @@ end transmitter;
 architecture behavioral of transmitter is
   
   -- Output shift register (containing also start and stop bit).
-  signal tx_shift_reg : std_logic_vector (9 downto 0);
+  signal tx_shift_reg : std_logic_vector (9 downto 0) := "1111111111";
   -- Register parallel to the output shift register where '1' shows the last
   -- bit of the frame ('1' is in the place of stop bit).
-  signal tx_flag      : std_logic_vector (9 downto 0);
+  signal tx_flag      : std_logic_vector (9 downto 0) := "0000000000";
   -- Transmitting of new frame could be started with next clk.
-  signal tx_ready     : std_logic;
+  signal tx_ready     : std_logic := '1';
 
 --------------------------------------------------------------------------------
 
diff --git a/tx_control.vhd b/tx_control.vhd
index d7c4f25..f3294c9 100644
--- a/tx_control.vhd
+++ b/tx_control.vhd
@@ -27,7 +27,7 @@ architecture behavioral of tx_control is
   
   type state_t is (waiting, next_frame, transmitting);
   
-  signal state : state_t;
+  signal state : state_t := waiting;
 
 --------------------------------------------------------------------------------
 
diff --git a/uart.vhd b/uart.vhd
index 11eb9b2..09450f9 100644
--- a/uart.vhd
+++ b/uart.vhd
@@ -129,9 +129,9 @@ architecture dataflow of uart is
   signal reg_re_b : boolean_vector (512 downto 0);
 
   
-  signal reg_baud : std_logic_vector (15 downto 0) := "0000000000000010";
+  signal reg_baud : std_logic_vector (15 downto 0) := (others => '0');
   signal reg_stat : std_logic_vector (7 downto 0);
-  signal reg_ie   : std_logic_vector (7 downto 0);
+  signal reg_ie   : std_logic_vector (7 downto 0) := (others => '0');
 
   
   signal tx_clk        : std_logic;