X-Git-Url: http://rtime.felk.cvut.cz/gitweb/fpga/uart.git/blobdiff_plain/a1d94cc6bbfe56f8e7b90d1f870db3fed5a86dea..584557d9d1b75aec4196c39d12560f7784ec4174:/baud_gen.vhd

diff --git a/baud_gen.vhd b/baud_gen.vhd
index 81dfa5c..b752d08 100644
--- a/baud_gen.vhd
+++ b/baud_gen.vhd
@@ -47,8 +47,8 @@ end baud_gen;
 
 architecture behavioral of baud_gen is
 
-  signal counter    : std_logic_vector (SCALE_WIDTH-1 downto 0);
-  signal clk_baud_s : std_logic;
+  signal counter    : std_logic_vector (SCALE_WIDTH-1 downto 0) := (others => '0');
+  signal clk_baud_s : std_logic := '0';
 
 --------------------------------------------------------------------------------
 
@@ -56,22 +56,24 @@ begin
 
   process (clk, reset)
   begin
-    if (reset = '1') then
-      counter <= (others => '0');
-      clk_baud_s <= '0';
-      
-    elsif (rising_edge(clk)) then
-      if (clk_baud_s = '0' and ce = '0') then
+    if (rising_edge(clk)) then
+      if (reset = '1') then
         counter <= (others => '0');
+        clk_baud_s <= '0';
 
       else
-        if (counter = 0) then
-          counter    <= scale;
-          clk_baud_s <= not clk_baud_s;
+        if (clk_baud_s = '0' and ce = '0') then
+          counter <= (others => '0');
 
         else
-          counter <= counter - 1;
+          if (counter = 0) then
+            counter    <= scale;
+            clk_baud_s <= not clk_baud_s;
 
+          else
+            counter <= counter - 1;
+
+          end if;
         end if;
       end if;
     end if;