Receiver control FSM prototype.

[fpga/uart.git] / baud_gen.vhd

diff --git a/baud_gen.vhd b/baud_gen.vhd
index 20f80100b09b9cf8b6b4c21cd8f94a3614aeee01..e778c713a4bafe609732387a12b0d1284b6ca017 100644 (file)
--- a/baud_gen.vhd
+++ b/baud_gen.vhd
@@ -3,6 +3,27 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
+--------------------------------------------------------------------------------
+-- Baud generator is an adjustable clock frequency divider. Division factor
+-- is determined by the value present on the input vector named 'scale' and is
+-- equal to:
+--              f_OUT = f_IN / (2 * (1 + 'scale'))
+--
+-- The divided clock signal has a duty cycle of 50%.
+--
+-- The reset input signal is asynchronous. When held active, the output is 0.
+-- When released, the output starts a new period and goes high with the next 
+-- rising edge of the input clock signal.
+--
+--             _   _   _   _   _   _   _   _   _   _   _   _
+--  CLK      _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
+--                        _________
+--  RESET    ____________|         |__________________________
+--             ___     __              ___     ___     ___ 
+--  CLK_BAUD _|   |___|  |____________|   |___|   |___|   |___
+--
+--------------------------------------------------------------------------------
+
 entity baud_gen is
   generic (
     SCALE_WIDTH : integer := 16