Some comments added.

[fpga/uart.git] / tx_control.vhd

diff --git a/tx_control.vhd b/tx_control.vhd
index 155605b8e3928261bf508bcebca75235e05158ed..d7c4f25847924a79056a5445510b4a8764cc8e6e 100644 (file)
--- a/tx_control.vhd
+++ b/tx_control.vhd
@@ -3,6 +3,13 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
+--------------------------------------------------------------------------------
+-- Transmitter control FSM
+--
+-- Finite state machine controlling interconnection of FIFO buffer and output
+-- shift register.
+--------------------------------------------------------------------------------
+
 entity tx_control is
   port (
     clk        : in  std_logic;