process (clk, reset) is
begin
- if reset = '1' then
- rx_ready <= '1';
- rx_running <= '0';
-
- bad_stop_bit <= '0';
- bad_start_bit <= '0';
+ if clk'event and clk = '0' then
+ if reset = '1' then
+ rx_ready <= '1';
+ rx_running <= '0';
+
+ bad_stop_bit <= '0';
+ bad_start_bit <= '0';
- elsif clk'event and clk = '0' then
- -- Start receiving a new frame
- if rx_ready = '1' and en = '1' then
- rx_shift_reg <= rx & rx_shift_reg (9 downto 1);
- rx_flag <= "0100000000";
- rx_ready <= '0';
- rx_running <= '1';
+ else
+ -- Start receiving a new frame
+ if rx_ready = '1' and en = '1' then
+ rx_shift_reg <= rx & rx_shift_reg (9 downto 1);
+ rx_flag <= "0100000000";
+ rx_ready <= '0';
+ rx_running <= '1';
- bad_start_bit <= rx;
- bad_stop_bit <= '0';
+ bad_start_bit <= rx;
+ bad_stop_bit <= '0';
- -- Receiving of the 1st data bit and all its consequents
- elsif rx_running = '1' then
- rx_shift_reg <= rx & rx_shift_reg (9 downto 1);
- rx_flag <= '0' & rx_flag (9 downto 1);
+ -- Receiving of the 1st data bit and all its consequents
+ elsif rx_running = '1' then
+ rx_shift_reg <= rx & rx_shift_reg (9 downto 1);
+ rx_flag <= '0' & rx_flag (9 downto 1);
- -- End of the frame is comming
- if rx_flag (0) = '1' then
- rx_ready <= '1';
- rx_running <= '0';
+ -- End of the frame is comming
+ if rx_flag (0) = '1' then
+ rx_ready <= '1';
+ rx_running <= '0';
- bad_stop_bit <= not rx;
+ bad_stop_bit <= not rx;
+ end if;
end if;
end if;
-
end if;
end process;