library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity uart is
  generic (
    output_fifo_width : integer := 2
  );
  port (
    mclk        : in  std_logic;
    per_addr    : in  std_logic_vector (7  downto 0);
    per_din     : in  std_logic_vector (15 downto 0);  -- unused
    per_en      : in  std_logic;
    per_wen     : in  std_logic_vector (1  downto 0);  -- unused
    puc         : in  std_logic;                       -- unused
    --per_irq_acc : in  std_logic;                       -- unused
    --per_irq     : out std_logic;
    per_dout    : out std_logic_vector (15 downto 0);

    txd         : out std_logic
  );
end uart;

-- Registers:
--  - Prescaler .16b
--  - Modulator .8b
--  - TX data .8b
--  - TX enable
--  - TX buffer full .1b
--  - TX buffer empty .1b
--  - TX buffer empty IE 1.b
--  - RX data .8b
--  - RX enable
--  - RX buffer empty .1b
--  - RX buffer half full .1b
--  - RX buffer full .1b
--  - RX buffer half full IE .1b
--  - RX buffer full IE .1b
--  - RX framing error .1b
--  - RX buffer overflow .1b

--------------------------------------------------------------------------------

architecture dataflow of uart is

  component tx_control is
    port (
      clk        : in  std_logic;
      reset      : in  std_logic;
      tx_ready   : in  std_logic;
      fifo_empty : in  std_logic;
      tx_we      : out std_logic;
      fifo_pop   : out std_logic
    );
  end component;

  component transmitter is
    port (
      clk    : in  std_logic;
      reset  : in  std_logic;
      data   : in  std_logic_vector (7 downto 0);
      we     : in  std_logic;
      ready  : out std_logic;
      tx     : out std_logic
    );
  end component;

  component fifo is
    generic (
      width : integer := 2
    );
    port (
      clk      : in  std_logic;
      reset    : in  std_logic;
      we       : in  std_logic;
      re       : in  std_logic;
      clear_ow : in  std_logic;
      d_in     : in  std_logic_vector (7 downto 0);
      d_out    : out std_logic_vector (7 downto 0);
      full     : out std_logic;
      hfull    : out std_logic;
      empty    : out std_logic;
      overflow : out std_logic
    );
  end component;

  component baud_gen is
    port (
      clk      : in  std_logic;
      ce       : in  std_logic;
      reset    : in  std_logic;
      scale    : in std_logic_vector (15 downto 0);
      clk_baud : out  std_logic
    );
  end component;

--------------------------------------------------------------------------------

  type boolean_vector is array (natural range <>) of boolean;

--------------------------------------------------------------------------------
  
  constant base_addr : integer := 16#0100#;
  
  constant UBAUD : integer := base_addr + 00;
  constant UTX   : integer := base_addr + 02;

  signal reg_we : std_logic_vector (511 downto 0);
  signal reg_re : boolean_vector (511 downto 0);

  signal tx_clk : std_logic;
  signal tx_data : std_logic_vector (7 downto 0);
  signal tx_we : std_logic;
  signal tx_ready : std_logic;

  signal tx_fifo_empty : std_logic;
  signal tx_fifo_re : std_logic;
  signal tx_fifo_we : std_logic;

--------------------------------------------------------------------------------

begin

  process (per_addr, per_wen, per_en)
  begin
    for i in reg_re'range loop
      reg_re (i) <= false;
      reg_we (i) <= '0';
      
      if (per_en = '1' and per_addr = i/2) then
        reg_re (i) <= true;
        
        if (per_wen (i mod 2) = '1') then
          reg_we (i) <= '1';
        end if;
      end if;
    end loop;
  end process;
  

  tx_control_0 : tx_control port map (
    clk        => mclk,
    reset      => puc,
    tx_ready   => tx_ready,
    fifo_empty => tx_fifo_empty,
    tx_we      => tx_we,
    fifo_pop   => tx_fifo_re
  );

  transmitter_0 : transmitter port map (
    clk    => tx_clk,
    reset  => puc,
    data   => tx_data,
    we     => tx_we,
    ready  => tx_ready,
    tx     => txd
  );

  tx_fifo : fifo port map (
    clk      => mclk,
    reset    => puc,
    we       => tx_fifo_we,
    re       => tx_fifo_re,
    clear_ow => '0',
    d_in     => per_din (7 downto 0),
    d_out    => tx_data,
    full     => open,
    hfull    => open,
    empty    => tx_fifo_empty,
    overflow => open
  );

  baud_gen_0 : baud_gen port map (
    clk      => mclk,
    ce       => '1',
    reset    => puc,
    scale    => "0000000000000000",
    clk_baud => tx_clk
  );


--------------------------------------------------------------------------------

  tx_fifo_we <= reg_we (UTX);
  
end dataflow;