library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--------------------------------------------------------------------------------
-- Output shift register
--
-- This entity can be used for generating of RS232 like output. Configuration is
-- hard wired as 8N1 (8 bits of data, no parity, 1 stop bit).
--
-- All operations (except for 'reset') are synchronous to 'clk' rising edges.
-- This clock signal also determines baud rate.
--
-- When 'ready' signal is high, next data vector can be written in by setting
-- 'we' signal.
--------------------------------------------------------------------------------

entity transmitter is
  port (
    clk    : in  std_logic;
    reset  : in  std_logic;
    data   : in  std_logic_vector (7 downto 0);
    we     : in  std_logic;
    ready  : out std_logic;
    tx     : out std_logic
  );
end transmitter;

--------------------------------------------------------------------------------

architecture behavioral of transmitter is
  
  -- Output shift register (containing also start and stop bit).
  signal tx_shift_reg : std_logic_vector (9 downto 0) := "1111111111";
  -- Register parallel to the output shift register where '1' shows the last
  -- bit of the frame ('1' is in the place of stop bit).
  signal tx_flag      : std_logic_vector (9 downto 0) := "0000000000";
  -- Transmitting of new frame could be started with next clk.
  signal tx_ready     : std_logic := '1';

--------------------------------------------------------------------------------

begin

  process (clk, reset)
  begin
    if (rising_edge(clk)) then
      if (reset = '1') then
        tx_shift_reg <= "1111111111";
        tx_flag <= "0000000000";
        tx_ready <= '1';
      
      else  
        if (we = '1') then
          tx_shift_reg <= '1' & data & '0';
          tx_flag <= "1000000000";
          tx_ready <= '0';
          
        else
          tx_shift_reg <= '1' & tx_shift_reg(9 downto 1);
          tx_flag <= '0' & tx_flag(9 downto 1);
          
          if (tx_flag(1) = '1') then
            tx_ready <= '1';
          end if;
          
        end if;
      end if;
    end if;
  end process;

--------------------------------------------------------------------------------

  ready <= tx_ready;
  
  tx <= tx_shift_reg(0);
  
end behavioral;