library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity transmitter is
  port (
    clk    : in  std_logic;
    reset  : in  std_logic;
    data   : in  std_logic_vector (7 downto 0);
    we     : in  std_logic;
    ready  : out std_logic;
    tx     : out std_logic
  );
end transmitter;

--------------------------------------------------------------------------------

architecture dataflow of transmitter is
  
  -- Output shift register (containing also start and stop bit).
  signal tx_shift_reg : std_logic_vector (9 downto 0);
  -- Register parallel to the output shift register where '1' shows the last
  -- bit of the frame ('1' is in the place of stop bit).
  signal tx_flag      : std_logic_vector (9 downto 0);
  -- Transmitting of new frame could be started with next tx_clk.
  signal tx_ready     : std_logic;

--------------------------------------------------------------------------------

begin

  process (clk, reset)
  begin
    if (reset = '1') then
      tx_shift_reg <= "1111111111";
      tx_flag <= "0000000000";
      tx_ready <= '1';
      
    elsif (rising_edge(clk)) then
      if (we = '1') then
        tx_shift_reg <= '1' & data & '0';
        tx_flag <= "1000000000";
        tx_ready <= '0';
        
      else
        tx_shift_reg <= '1' & tx_shift_reg(9 downto 1);
        tx_flag <= '0' & tx_flag(9 downto 1);
        
        if (tx_flag(1) = '1') then
          tx_ready <= '1';
        end if;
        
      end if;
    end if;
  end process;

--------------------------------------------------------------------------------

  ready <= tx_ready;
  
  tx <= tx_shift_reg(0);
  
end dataflow;