library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity tb_tx is
end tb_tx;


architecture testbench of tb_tx is

  component transmitter is
    port (
      clk    : in  std_logic;
      reset  : in  std_logic;
      data   : in  std_logic_vector (7 downto 0);
      we     : in  std_logic;
      ready  : out std_logic;
      tx     : out std_logic
    );
  end component;
  
  signal clk   : std_logic;
  signal reset : std_logic;
  signal data  : std_logic_vector (7 downto 0) := (others => '0');
  signal we    : std_logic := '0';
  signal ready : std_logic;
  signal tx    : std_logic;
  
  constant period : time := 2 us;
  constant offset : time := 2 us;
  
begin
  UUT : transmitter port map (
    clk   => clk,
    reset => reset,
    data  => data,
    we    => we,
    ready => ready,
    tx    => tx
  );

  process
  begin
    clk <= '0';
    wait for offset;
    
    loop
      clk <= '1';
      wait for period/2;
      clk <= '0';
      wait for period/2;
    end loop;
  end process;


  process
  begin
    reset <= '0';
    wait for 1.5 * period;
    reset <= '1';
    wait for 1 * period;
    reset <= '0';
    wait;
  end process;


  process
  begin
    wait until reset = '0';
    wait for 0.1 * period;
    
    wait until ready = '1';
    data <= "01000001";
    we <= '1';
    wait until ready = '0';
    data <= "00000000";
    we <= '0';
    

    wait until ready = '1';
    wait for 1.5 * period;
    data <= "01000010";
    we <= '1';
    wait until ready = '0';
    data <= "00000000";
    we <= '0';
    
    wait;
  end process;
  
end testbench;