library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity tb_uart is
end tb_uart;


architecture testbench of tb_uart is

  component uart is
    generic (
      output_fifo_width : integer
    );
    port (
      mclk        : in  std_logic;
      per_addr    : in  std_logic_vector (7  downto 0);
      per_din     : in  std_logic_vector (15 downto 0);
      per_en      : in  std_logic;
      per_wen     : in  std_logic_vector (1  downto 0);
      puc         : in  std_logic;
      --per_irq_acc : in  std_logic;
      --per_irq     : out std_logic;
      per_dout    : out std_logic_vector (15 downto 0);

      txd         : out std_logic
    );
  end component;  
  
  signal clk   : std_logic;
  signal reset : std_logic;
  
  constant period : time := 1 us;
  constant offset : time := 2 us;


  signal per_addr : std_logic_vector (7  downto 0);
  signal per_din  : std_logic_vector (15 downto 0);
  signal per_en   : std_logic;
  signal per_wen  : std_logic_vector (1  downto 0);
  signal per_dout : std_logic_vector (15 downto 0);

  signal txd      : std_logic;


  type test_record is record
    we : std_logic;
    word : std_logic;
    data : std_logic_vector (15 downto 0);
    addr : std_logic_vector (15 downto 0);
  end record;
  
  type test_array is array (positive range <>) of test_record;
  
  constant test_vectors : test_array := (
    ('1','1',X"0002",X"0100"),
    ('1','0',X"0065",X"0102")
  );

--------------------------------------------------------------------------------

begin
  UUT : uart port map (
    mclk      => clk,
    per_addr  => per_addr,
    per_din   => per_din,
    per_en    => per_en,
    per_wen   => per_wen,
    puc       => reset,
    per_dout  => per_dout,

    txd       => txd
  );


  process
  begin
    clk <= '0';
    wait for offset;
    
    loop
      clk <= '1';
      wait for period/2;
      clk <= '0';
      wait for period/2;
    end loop;
  end process;


  process
  begin
    reset <= '0';
    wait for period;
    reset <= '1';
    wait for period;
    reset <= '0';
    wait;
  end process;


  process
    variable vector : test_record;
  begin
    per_addr <= X"00";
    per_din  <= X"0000";
    per_en   <= '0';
    per_wen  <= "00";

    wait for 3.1 * period;


    for i in test_vectors'range loop
      vector := test_vectors(i);

      per_addr <= vector.addr (8 downto 1);
      per_en <= '1';
    
      if (vector.word = '1') then
        per_wen <= "11";
        per_din <= vector.data (15 downto 0);
        
      else    
        if (vector.addr(0) = '1') then
          per_wen <= "10";
          per_din <= vector.data (7 downto 0) & "00000000";
        else
          per_wen <= "01";
          per_din <= "00000000" & vector.data (7 downto 0);
        end if;
      end if;
      
      wait for period;
      
      per_addr <= X"00";
      per_din <= X"0000";
      per_en <= '0';
      per_wen <= "00";
    end loop;

    wait;
  end process;
  
end testbench;