From: Vladimir Burian Date: Sat, 26 Mar 2011 14:41:02 +0000 (+0100) Subject: Added irc_dump. X-Git-Url: http://rtime.felk.cvut.cz/gitweb/fpga/pwm.git/commitdiff_plain/5233bf3691f47f206c4b58a75a0ee087fed8fd48 Added irc_dump. --- diff --git a/irc_dump.vhd b/irc_dump.vhd new file mode 100644 index 0000000..3317b00 --- /dev/null +++ b/irc_dump.vhd @@ -0,0 +1,62 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +-------------------------------------------------------------------------------- + +entity irc_dump is + generic ( + IRF_ADR_W : integer := 5; + IRC_BASE : integer := 1); + port ( + -- Primary slave intefrace + ACK_O : out std_logic; + CLK_I : in std_logic; + RST_I : in std_logic; + STB_I : in std_logic; + -- IRC interface + IRC_DAT_I : in std_logic_vector (15 downto 0); + -- Shared dual-port memory + IRF_ACK_I : in std_logic; + IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0); + IRF_DAT_O : out std_logic_vector (15 downto 0); + IRF_STB_O : out std_logic; + IRF_WE_O : out std_logic); +end entity irc_dump; + +-------------------------------------------------------------------------------- + +architecture behavioral of irc_dump is + + subtype irf_adr_t is std_logic_vector (IRF_ADR_W-1 downto 0); + + constant IRC_ADR : irf_adr_t := conv_std_logic_vector(IRC_BASE, IRF_ADR_W); + + signal INNER_ACK : std_logic; + +-------------------------------------------------------------------------------- + +begin + + ACK_O <= STB_I; + + IRF_DAT_O <= IRC_DAT_I; + + IRF_ADR_O <= IRC_ADR; + IRF_STB_O <= STB_I and not INNER_ACK; + IRF_WE_O <= STB_I and not INNER_ACK; + + + process (CLK_I, RST_I) is + begin + if RST_I = '1' then + INNER_ACK <= '0'; + + elsif rising_edge(CLK_I) then + INNER_ACK <= STB_I; + end if; + end process; + +end architecture behavioral; + diff --git a/mcc.vhd b/mcc.vhd index 2bda9c9..47ebe0a 100644 --- a/mcc.vhd +++ b/mcc.vhd @@ -72,6 +72,10 @@ architecture behavioral of mcc is signal PWM_SL_STB_I : std_logic; signal PWM_SL_MUX_CODE : std_logic_vector (1 downto 0); + signal IRC_IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0); + signal IRC_IRF_DAT_O : std_logic_vector (15 downto 0); + signal IRC_IRF_STB_O : std_logic; + signal IRC_IRF_WE_O : std_logic; type state_t is (ready, read_mask, do_mcc, done); @@ -89,21 +93,25 @@ architecture behavioral of mcc is begin IRF_ADR_O <= MASTER_IRF_ADR_O when MCC_MUX_EN = '0' else + IRC_IRF_ADR_O when MCC_MUX_CODE = 0 else VECTOR_IRF_ADR_O when MCC_MUX_CODE = 2 else PWM_IRF_ADR_O when MCC_MUX_CODE = 5 else (others => '-'); IRF_DAT_O <= MASTER_IRF_DAT_O when MCC_MUX_EN = '0' else + IRC_IRF_DAT_O when MCC_MUX_CODE = 0 else VECTOR_IRF_DAT_O when MCC_MUX_CODE = 2 else PWM_IRF_DAT_O when MCC_MUX_CODE = 5 else (others => '-'); IRF_STB_O <= MASTER_IRF_STB_O when MCC_MUX_EN = '0' else + IRC_IRF_STB_O when MCC_MUX_CODE = 0 else VECTOR_IRF_STB_O when MCC_MUX_CODE = 2 else PWM_IRF_STB_O when MCC_MUX_CODE = 5 else '0'; IRF_WE_O <= MASTER_IRF_WE_O when MCC_MUX_EN = '0' else + IRC_IRF_WE_O when MCC_MUX_CODE = 0 else VECTOR_IRF_WE_O when MCC_MUX_CODE = 2 else '0'; @@ -134,6 +142,22 @@ begin IRF_STB_O => MASTER_IRF_STB_O, IRF_WE_O => MASTER_IRF_WE_O); + irc_dump_1 : entity work.irc_dump + generic map ( + IRF_ADR_W => IRF_ADR_W, + IRC_BASE => 16#01#) + port map ( + ACK_O => MCC_ACK (0), + CLK_I => CLK_I, + RST_I => RST_I, + STB_I => MCC_STB (0), + IRC_DAT_I => IRC_DAT_I, + IRF_ACK_I => IRF_ACK_I, + IRF_ADR_O => IRC_IRF_ADR_O, + IRF_DAT_O => IRC_IRF_DAT_O, + IRF_STB_O => IRC_IRF_STB_O, + IRF_WE_O => IRC_IRF_WE_O); + vector_gen_1 : entity work.vector_gen generic map ( A_BASE => 16#04#, diff --git a/tb/Makefile b/tb/Makefile index 0dfbf20..ee49ed9 100644 --- a/tb/Makefile +++ b/tb/Makefile @@ -11,6 +11,7 @@ VHDL_ENTITIES = counter.o \ mcc_master.o \ sequencer.o \ pwm_dump.o \ + irc_dump.o \ mcc.o diff --git a/tb/tb_mcc.sav b/tb/tb_mcc.sav index f805787..5bcefb9 100644 --- a/tb/tb_mcc.sav +++ b/tb/tb_mcc.sav @@ -9,8 +9,12 @@ clk_i rst_i stb_i ack_o +@23 +irc_dat_i[15:0] +@28 dbg_mem00[15:0] @22 +dbg_mem01[15:0] dbg_mem04[15:0] dbg_mem11[15:0] dbg_mem15[15:0] diff --git a/tb/tb_mcc.vhd b/tb/tb_mcc.vhd index 03d7059..3b49380 100644 --- a/tb/tb_mcc.vhd +++ b/tb/tb_mcc.vhd @@ -38,10 +38,13 @@ architecture testbench of tb_mcc is signal LUT_DAT_I : std_logic_vector (LUT_DAT_W-1 downto 0); signal LUT_STB_O : std_logic; + signal IRC_DAT_I : std_logic_vector (15 downto 0); + subtype word_t is std_logic_vector (15 downto 0); - signal dbg_mem00 : word_t := "0000000000100100"; -- MCC enable flags (RO) + signal dbg_mem00 : word_t := "0000000000100101"; -- MCC enable flags (RO) + signal dbg_mem01 : word_t := (others => '0'); -- IRC signal dbg_mem04 : word_t := (others => '0'); -- Angle (RO) signal dbg_mem11 : word_t := (others => '0'); -- Phase 1 signal dbg_mem15 : word_t := (others => '0'); -- Phase 2 @@ -65,7 +68,7 @@ begin LUT_STB_O => LUT_STB_O, LUT_ADR_O => LUT_ADR_O, LUT_DAT_I => LUT_DAT_I, - IRC_DAT_I => (others => '0'), + IRC_DAT_I => IRC_DAT_I, PWM_DAT_O => open, PWM1_STB_O => open, PWM2_STB_O => open, @@ -128,6 +131,7 @@ begin if IRF_WE_O = '0' then case conv_integer(IRF_ADR_O) is when 16#00# => IRF_DAT_I <= dbg_mem00; + when 16#01# => IRF_DAT_I <= dbg_mem01; when 16#04# => IRF_DAT_I <= dbg_mem04; when 16#11# => IRF_DAT_I <= dbg_mem11; when 16#15# => IRF_DAT_I <= dbg_mem15; @@ -136,6 +140,7 @@ begin end case; else case conv_integer(IRF_ADR_O) is + when 16#01# => dbg_mem01 <= IRF_DAT_O; when 16#11# => dbg_mem11 <= IRF_DAT_O; when 16#15# => dbg_mem15 <= IRF_DAT_O; when 16#19# => dbg_mem19 <= IRF_DAT_O; @@ -149,7 +154,8 @@ begin UUT_FEED : process is begin - STB_I <= '0'; + STB_I <= '0'; + IRC_DAT_I <= "0000000010101010"; wait for offset; wait for 4*period; @@ -157,6 +163,8 @@ begin for i in 0 to 1 loop dbg_mem04 <= conv_std_logic_vector(i, 16); + IRC_DAT_I <= conv_std_logic_vector(i, 16); + STB_I <= '1'; wait until rising_edge(CLK_I) and ACK_O = '1'; STB_I <= '0';