X-Git-Url: http://rtime.felk.cvut.cz/gitweb/fpga/pwm.git/blobdiff_plain/c26e6a9e583080feb50569e815aa4c5be5324dfe..HEAD:/mcc_master.vhd

diff --git a/mcc_master.vhd b/mcc_master.vhd
index 12d5b94..fca6652 100644
--- a/mcc_master.vhd
+++ b/mcc_master.vhd
@@ -15,21 +15,21 @@ entity mcc_master is
     IRF_ADR_W : integer := 5);
   port (
     -- Primary slave intefrace
-    ACK_O        : out std_logic;
+    ACK_O        : out std_logic := '0';
     CLK_I        : in  std_logic;
     RST_I        : in  std_logic;
     STB_I        : in  std_logic;
     -- Motion Control Chain
-    MCC_STB_O    : out std_logic_vector (MCC_W-1 downto 0);
+    MCC_STB_O    : out std_logic_vector (MCC_W-1 downto 0) := (others => '0');
     MCC_ACK_I    : in  std_logic_vector (MCC_W-1 downto 0);
-    MCC_MUX_CODE : out std_logic_vector (MUX_W-1 downto 0);
-    MCC_MUX_EN   : out std_logic;
+    MCC_MUX_CODE : out std_logic_vector (MUX_W-1 downto 0) := (others => '0');
+    MCC_MUX_EN   : out std_logic := '0';
     -- Shared dual-port memory
     IRF_ACK_I    : in  std_logic;
     IRF_ADR_O    : out std_logic_vector (IRF_ADR_W-1 downto 0);
     IRF_DAT_I    : in  std_logic_vector (15 downto 0);
     IRF_DAT_O    : out std_logic_vector (15 downto 0);
-    IRF_STB_O    : out std_logic;
+    IRF_STB_O    : out std_logic := '0';
     IRF_WE_O     : out std_logic);
 end entity mcc_master;
 
@@ -39,13 +39,13 @@ architecture behavioral of mcc_master is
 
   type state_t is (ready, read_mask, do_mcc, done);
 
-  signal state : state_t;
+  signal state : state_t := ready;
 
   signal mcc_mask       : std_logic_vector (MCC_W-1 downto 0);
-  signal mcc_ack_inner  : std_logic_vector (MCC_W downto 0);
-  signal mcc_stb_inner  : std_logic_vector (MCC_W-1 downto 0);
+  signal mcc_ack_inner  : std_logic_vector (MCC_W downto 0) := (others => '0');
+  signal mcc_stb_inner  : std_logic_vector (MCC_W-1 downto 0) := (others => '0');
   signal mux_code_inner : std_logic_vector (MUX_W-1 downto 0);
-  signal mcc_exec       : std_logic;
+  signal mcc_exec       : std_logic := '0';
   
 --------------------------------------------------------------------------------
 
@@ -67,27 +67,29 @@ begin
 
   MCC_EXEC_LOGIC : process (RST_I, CLK_I) is
   begin
-    if RST_I = '1' then
-      mcc_ack_inner <= (others => '0');
-      mcc_stb_inner <= (others => '0');
-
-    elsif rising_edge(CLK_I) then
-      if mcc_exec = '0' then
+    if rising_edge(CLK_I) then
+      if RST_I = '1' then
         mcc_ack_inner <= (others => '0');
         mcc_stb_inner <= (others => '0');
-        
+
       else
-        mcc_ack_inner (0) <= mcc_exec;
-        
-        for i in 0 to MCC_W-1 loop
-          if mcc_mask (i) = '1' then
-            mcc_ack_inner (i+1) <= MCC_ACK_I (i);
-            mcc_stb_inner (i)   <= mcc_ack_inner (i);
-          else
-            mcc_ack_inner (i+1) <= mcc_ack_inner (i);
-            mcc_stb_inner (i)   <= '0';
-          end if;
-        end loop;
+        if mcc_exec = '0' then
+          mcc_ack_inner <= (others => '0');
+          mcc_stb_inner <= (others => '0');
+          
+        else
+          mcc_ack_inner (0) <= mcc_exec;
+          
+          for i in 0 to MCC_W-1 loop
+            if mcc_mask (i) = '1' then
+              mcc_ack_inner (i+1) <= MCC_ACK_I (i);
+              mcc_stb_inner (i)   <= mcc_ack_inner (i);
+            else
+              mcc_ack_inner (i+1) <= mcc_ack_inner (i);
+              mcc_stb_inner (i)   <= '0';
+            end if;
+          end loop;
+        end if;
       end if;
     end if;
   end process;